A Data Reuse Method to Eliminate Fetch Conflicts for Coarse-grained Reconfigurable Structures

Abstract

A method for data reuse and elimination of memory access conflicts for coarse-grained reconfigurable structures. A loop transformation model that maximizes effective data reuse for perfectly nested loop kernels is proposed to maximize the data available between iterations during program execution. Reuse, as well as the configuration file change strategy in the code generation phase, eliminate redundant memory access operations in data reuse pairs, and reduce memory access conflicts during loop execution.

Description

technical field [0001] The present application relates to the field of coarse-grained reconfigurable structure compilers, and in particular, relates to a loop transformation model aimed at maximizing effective data reuse of reconfigurable structures and a configuration file modification strategy used in the code generation phase. Background technique [0002] Coarse-Grained Reconfigurable Architecture (CGRA) is a new hardware architecture with higher energy efficiency. It is mainly used for hardware acceleration of computing-intensive applications, such as video processing and neural network operations. After research and investigation, it is found that the application execution time is mainly consumed in the core part of the program loop. Reference ADRES [1] model gives a typical CGRA structure, such as figure 1 shown. The compiler abstracts the core part of the program loop as a data flow graph (data flow graph, DFG), and maps it to different processing elements (proces...

AI Technical Summary

Problems solved by technology

However, none of the above studies considered ways to reduce the number of memory access operations to reduce memory access conflicts

Images