Flash memory array
A flash memory array and flash memory cell technology, applied in the semiconductor field, can solve problems such as unfavorable memory reliability, reduced process size and cell area, complex process, etc., and achieve the effect of good process compatibility and miniaturization characteristics
Pending Publication Date: 2021-11-23
BEIJING PANXIN MICROELECTRONICS TECH CO LTD
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Problems solved by technology
[0004] However, the floating gate flash memory has the following disadvantages: the process is relatively complicated; the vertical height of the gate structure is increased due to the existence of the floating gate structure in the flash memory unit, which is not conducive to scaling down the process size and cell area; Conductivity, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory
However, the source lines of existing flash memory arrays are formed in the active area, and the sheet resistance of the active area is much higher than that of metal
Therefore, in order to reduce the series resistance of the source lines, it is necessary to short-circuit the source lines in the active area through metal common source lines every few rows or columns in the row or column direction, resulting in an increase in the area overhead of the flash memory array.
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[0024] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, "implementation" and "implementation" are interchangeable words that are non-limiting examples of devices or methods that employ one or more of the inventive concepts disclosed herein. It is evident, however, that the exemplary embodiments may be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the exemplary embodiments. Furthermore, each exemplary embodiment may be different, but is not necessarily exclusive. For example, the specific shapes, configurations and characteristics of the exemplary embodiments can be used or implemented in other exemplary embodiments without departing...
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The invention provides a flash memory array. The flash memory array comprises a plurality of flash memory units which are arranged along a row direction and a column direction vertical to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending along the column direction, in which a flash memory unit pair is disposed at an intersection point of the word line group and the bit line group, the flash memory unit pair comprising a first flash memory unit and a second flash memory unit which are adjacent in the row direction and share the same bit line group. According to the flash memory array disclosed by the invention, the arrangement density of the bit lines can be improved and the parasitic resistance of the bit lines can be reduced under the condition that the array size is not increased. In addition, compared with a flash memory array in the prior art, the flash memory array disclosed by the invention also has better process compatibility and miniaturization characteristic.
Description
technical field [0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a flash memory array. Background technique [0002] Flash memory, referred to as flash memory, is a non-volatile memory, that is, the stored data will not be lost even if the power is cut off, and it is especially suitable for mobile communication and computer storage components and other fields. In addition, some flash memories also have high-density storage capabilities, and are suitable for applications such as large-capacity mobile storage media. [0003] Conventional flash memory adopts a floating gate cell structure. The floating gate non-volatile memory originated from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor: Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. This structure adds a metal floating gate and an ultra-thin tunnel oxide layer on the basis of the ...
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Login to View More IPC IPC(8): G11C5/02G11C7/18G11C8/14
CPCG11C5/02G11C7/18G11C8/14
Inventor蒋家勇石振东
OwnerBEIJING PANXIN MICROELECTRONICS TECH CO LTD