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Decoder hardware architecture applied to concatenated codes of RS (Reed-Solomon) codes and BCH (Broadcast Channel) codes

A hardware architecture and decoder technology, applied in the field of optical communication encoding and decoding, to achieve the effect of small area and low power consumption

Pending Publication Date: 2022-04-12
南京风兴科技有限公司
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Problems solved by technology

[0004] However, for the current RS code and BCH code concatenated coding scheme, there is no corresponding decoder hardware architecture for decoding the RS code and BCH code concatenated code

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  • Decoder hardware architecture applied to concatenated codes of RS (Reed-Solomon) codes and BCH (Broadcast Channel) codes
  • Decoder hardware architecture applied to concatenated codes of RS (Reed-Solomon) codes and BCH (Broadcast Channel) codes
  • Decoder hardware architecture applied to concatenated codes of RS (Reed-Solomon) codes and BCH (Broadcast Channel) codes

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Embodiment Construction

[0027] For the convenience of explaining the technical solution of the application, a brief introduction of the concatenated coding scheme of the RS code and the BCH code involved in the application is given first.

[0028] Taking the 1600Gbps optical communication system as an example, two coding schemes in which RS codes and BCH codes are concatenated are introduced.

[0029] The first one uses RS (544,514) codes and BCH (360,340) codes for concatenated coding. Wherein, the outer code of concatenated code comprises the code word of 2 complete RS (544,514), specifically, a code word has 544 code elements, 514 information code elements; Wherein 1 code element is 1 symbol (symbol Number), 1symbol=10bits. The inner code adopts BCH(360,340), wherein one BCH codeword contains 340bits of code source information and 20bits of check bits, and a concatenated code requires 32 codewords of BCH(360,340) codes. The total length of the concatenated code is 360bits*32=11520bits. The spec...

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Abstract

The invention provides a decoder hardware architecture applied to cascade codes of RS codes and BCH codes. The decoder hardware architecture comprises a BCH decoding module, a first de-interleaver, an RS decoding module and a multiplexer, wherein the BCH decoding module and the RS decoding module adopt the same target total parallelism and the same target clock frequency. The decoding hardware architecture has the following beneficial effects: the decoding hardware architecture can realize decoding of RS code and BCH code cascade codes in an ultra-high-speed communication network of 800Gbps, 1600Gpbs and above, and can simultaneously meet the requirements of extremely high speed, small area and low power consumption on a decoder in commercial application.

Description

technical field [0001] The invention relates to the technical field of optical communication coding and decoding, in particular to a hardware architecture of a decoder applied to concatenated codes of RS codes and BCH codes. Background technique [0002] At present, the optical communication network is the most important communication carrier in the world, with the advantages of fast transmission speed, long transmission distance, strong anti-interference ability and low loss. However, in long-distance communication, due to the influence of factors such as attenuation and crosstalk, problems such as loss and error may occur in data transmission. Therefore, data is usually encoded before transmission to ensure the validity and reliability of data transmission. Nowadays, the data generated and transmitted all over the world is increasing rapidly. In order to realize ultra-high-speed optical communication, the bandwidth of the optical communication network currently being rese...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15H03M13/27
Inventor 陶为朱丹阳王中风
Owner 南京风兴科技有限公司
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