Regulation method and module for compressed bit stream calculation and storage requirement in video frequency decoder

A technology for storage requirements and decoders, applied in the field of multimedia audio-video coding and compression, can solve the problems of limiting the variability of graphic complexity, low average complexity, and different complexity

Inactive Publication Date: 2005-04-20
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The complexity distribution may be that the resources of the decoder are exhausted in an instant, while the average complexity is lower than the limit setting
Restricting the window to a short time limits the variability in graph complexity
This means that all graphs must have constant complexity
This is not a good idea, because by the nature of the encoding, different graphics types should have different complexities
[0011] The second reason is that complexity is not just about computation time
The second factor is the storage technology requirement, which is not captured in the complexity measure

Method used

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  • Regulation method and module for compressed bit stream calculation and storage requirement in video frequency decoder
  • Regulation method and module for compressed bit stream calculation and storage requirement in video frequency decoder
  • Regulation method and module for compressed bit stream calculation and storage requirement in video frequency decoder

Examples

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no. 1 example

[0058] The first embodiment is image 3 , 4 , 5, and 6. image 3 Representation and existing technology figure 2 The same figure, but with new parts added according to the invention. The first embodiment uses a virtual decoder 303. The cost function generator 302 does not directly feed back to the macroblock type determination module 301, but passes through the virtual decoder 303. The virtual decoder 303 also receives the appearance time stamp of the coded graphics. The virtual decoder 303 performs the functions as described above. It is a hypothetical module used to simulate a decoder with defined computing and memory resources. These resources are consumed according to the coding information found in the cost function generator and the presentation time stamp.

[0059] Figure 4 The function of the virtual decoder 303 is explained. The complexity cost function from the cost function generator 302 is transferred to the virtual VOP storage buffer 401, and the decoding time stam...

no. 2 example

[0082] The second embodiment describes the general operation of this embodiment.

[0083] The module is to simulate the role of the target decoder and some of its modules, such as bit stream buffer, central processing unit (CPU), or memory storage device. In order to ensure that a typical decoder decodes the bitstream generated by the encoder, during the generation of the encoded bitstream, the module can be used as an independent video verifier or embedded in a video verifier. The module can also be used as a standalone video verifier. An independent video checker is used to check and check the bit stream that has been encoded in some way to ensure that a typical decoder can decode it.

[0084] Picture 9 The illustrated embodiment represents a video verifier, which includes the following modules:

[0085] 1) Video buffer module 120,

[0086] 2) Video complexity module 130,

[0087] 3) Video reference memory module 140, and

[0088] 4) Video display module 150.

...

no. 3 example

[0111] The third embodiment is a generalized summary of the present invention. It describes an example of the complete technical specification of the video verifier module. It is segmented to illustrate the following definition:

[0112] Video buffer module definition

[0113] The Video Buffer Checker (VBV) is an algorithm used to check the transfer rate function R(t) of the bit stream and verify that the capacity of the rate buffer memory required in the decoder is less than the specified buffer capacity. According to MPEG-2, the new VBV is determined by pointing to new features of video coding. If the visual bitstream is composed of multiple video objects (VO), each with one or more video object layers (VOL), the rate buffer module is independently applied to each VOL (using the buffer specific to that VOL) Capacity and rate function).

[0114] VBV is suitable for the actual video being coded. This video coding is a combination of intra, predictive and bidirectional video target...

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Abstract

An apparatus for compressed video bitstream verification includes a set of verifier modules: Video Complexity Verifier (VCV), Video Memory Verifier (VMV) and Video Presentation Verifier (VPV). These modules specify the performance of decoders for variable VOP sizes and rates, and define new parameters and bounds to measure and verify the computational and storage resources required by the bitstream. These modules can be used for video encoders, or for inspection of pre-compressed video distributions.

Description

Technical field [0001] The invention relates to a method and a module for adjusting the calculation and storage requirements of a video decoder compressed bit stream. The present invention is applied to the field of multimedia audio-video coding and compression technology, where the encoder needs to adjust the complexity requirements of the bit stream it generates. This can ensure that a decoder that complies with the standard complexity specification can successfully decode these bit streams and not run without resources. Background technique [0002] In the past, the implementation of a video decoder that meets a specific performance of a standard needs to ensure that the decoder has sufficient resources to withstand the worst possible situation according to technical specifications. This is not a good engineering practice, because usually the worst-case scenario represents a situation that is almost impossible under normal working conditions. This leads to excessive engineerin...

Claims

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Application Information

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IPC IPC(8): H04N7/24H04N7/26
CPCH04N19/20H04N19/176H04N21/2662H04N21/8547
Inventor陈朝庆胡国荣
OwnerPANASONIC CORP