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Method for processor power-saving, recorded medium, and processor power-saving controller

A technology of a control method and a processing device, which is applied in the direction of data processing power supply, multi-programming device, electrical digital data processing, etc., and can solve the problems of maintaining power-saving mode and impossibility of high efficiency, etc.

Inactive Publication Date: 2002-05-15
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the conventional processor power-saving control method, the processing device 22 must be started every time a timer interrupt of each OS occurs, and there is a problem that it is impossible to efficiently maintain the power-saving mode.

Method used

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  • Method for processor power-saving, recorded medium, and processor power-saving controller
  • Method for processor power-saving, recorded medium, and processor power-saving controller
  • Method for processor power-saving, recorded medium, and processor power-saving controller

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] Fig. 2 is a conceptual diagram showing a power saving control device for a processor according to Embodiment 1 of the present invention. FIG. 3 is a flowchart illustrating the main OS processing procedure in the processing procedure of the processor power saving control method. FIG. 4 is a flowchart illustrating sub-OS processing steps and sub-OS interrupt steps in a processor power saving control method. In Fig. 2, 1 is the main OS that actually controls the hardware such as the processing device and timer; 2 is the processing device with power saving mode; 3 is the aperiodic interrupt to the main OS1, and the timing interrupt is performed only when the time elapsed notification is necessary. 4 is the timing processor of the main OS1 started according to the timing interrupt from the hardware timer 3; 5 is the main OS scheduler that executes tasks in order according to the call of the timing processor 4; 6 is the main OS scheduler in the The power saving mechanism of ...

Embodiment 2

[0067] Fig. 5 is a conceptual diagram showing a power saving control device for a processor according to Embodiment 2 of the present invention. FIG. 6 is a flow chart illustrating sub-OS processing steps and sub-OS interrupt steps in the processor power saving control method according to Embodiment 2 of the present invention. In Fig. 5, 14 is an alarm processor activated by the main OS1 which operates as a timer processor of the sub OS8. In Fig. 5, the same symbols as those in Fig. 2 denote the same or corresponding parts, and description thereof will be omitted.

[0068] Main OS processing steps and 3rd Figure 1 , the description is omitted. Next, the sub OS processing procedure and the sub OS interrupt procedure will be described with reference to FIG. 6 . The sub OS8 is processed as one of the tasks executed by the main OS1. When the sub OS8 starts up, the alarm handler 14 from the main OS1 is registered in S221. The alarm processor 14 has a function of performing the...

Embodiment 3

[0072] Fig. 7 is a conceptual diagram showing a power saving device for a processor according to Embodiment 3 of the present invention. FIG. 8 is a flow chart illustrating sub OS processing steps and sub OS interrupt steps in the processor power saving control method. In Fig. 7, 15 is a high-priority task activated by the main OS1 that operates as a timer processor of the sub OS8. The main OS1 executes tasks with high priority first, and the high priority task 15 must be set to a higher priority than the tasks of the sub OS8. In Fig. 7, the same symbols as those in Fig. 2 denote the same or corresponding parts, and description thereof will be omitted.

[0073] Main OS processing steps and 3rd Figure 1, the description is omitted. Next, the sub-OS processing procedure and the sub-OS interrupt procedure will be described with reference to FIG. 8. FIG. The sub OS8 is processed as one of the execution tasks of the main OS1. When the sub-OS 8 is activated, the high-priority t...

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PUM

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Abstract

In an environment where multiple OSs are present in one processor having a power saving function, a power-saving processor controller has a main OS that accepts a timer interrupt outputted from a hardware timer at a timing when a predetermined time elapses and a sub-OS treated as a task executed by the main OS, judges whether an executable task is present or not at the timing of the timer interrupt, and carries out an interrupt to the sub-OS if any executable task is present in the sub-OS.

Description

technical field [0001] The present invention relates to maintaining the power saving of the processor by avoiding individual timing interrupts by collectively controlling the timing interrupts of each OS in an environment where a plurality of OSs (Operating Systems) exist on one processing device having a power saving function. mode, realizes the power saving control method of the processor that suppresses power consumption. Background technique [0002] Portable information terminals such as portable phones and notebook computers use rechargeable batteries as power sources. However, in the case of continuous use of the terminal, the operating time of the terminal using the rechargeable battery is several hours at best. Therefore, in order to prolong the operating time of the terminal, it is necessary to improve the power saving function that can use battery power more effectively. As a power saving function, in the idle time, that is, when the processing device is not per...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/04G06F1/32G06F9/46
CPCG06F1/3228
Inventor 片山吉章
Owner MITSUBISHI ELECTRIC CORP