Device for controlling interior storage of chip and its storage method

Abstract

The present invention relates to an equipment for controlling on-chip storage of chip and its method. The equipment includes multichannel data buffer memory control/state unit, data RAM (random memory) reading-writing control unit, dual port data storage RAM adopting chained list type storage management, configuration RAM control unit and configuration RAM array. The described method includes thefollowing steps: firstly, the data operation command can be received by multichannel data buffer memory control/state unit; then according to the command and parameter information in the configuration RAM array the data RAM reading-writing control unit can make reading-writing operation in dual port data storage RAM; finally it also has need of updating correspondent configuration parameter information.

Description

technical field [0001] The invention relates to the technical field of computer communication, in particular to an on-chip storage device of a control chip and a storage method thereof. Background technique [0002] In communication equipment, a multi-channel control chip for caching data in the receiving or sending direction needs to be installed between the physical port and the data transmission bus, as shown in Figure 1, in order to reduce the number of applications and occupancy of data services on the data transmission bus and effectively utilize bandwidth. There are usually two solutions for the existing multi-channel control chip on-chip storage: one is to allocate the same size of storage space for each channel in an on-chip data cache, and each channel uses its own storage without distinction. The other is to use a data RAM for each physical port, and determine the respective data RAM capacity according to the fixed port rate. [0003] Although the circuit struct...

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Problems solved by technology

[0003] Although the circuit structure of the on-chip storage method that allocates storage space for each channel is relatively simple, it is easy to implement and verify, but it loses the ability to flexibly allocate the priority of on-chip cache and bus transmission according to the flow of logical channels , it is impossible to achieve the maximum performance of multi-channel processing with a small on-chip cache, especially in the case of cache and bus transmission of multi-channel data at different rates, the performance difference is very large

Moreover, in the on-chip storage method that allocates the same size storage space for each channel in an on-chip data cache, priority control for each channel is not provided, and it is difficult to achieve better results based on the limited size of the on-chip data cache. Adapt to the environment of multiple rate applications, and meet the higher requirements of channel control for different flows

[0004] And another on-chip storage method that configures a data RAM for each port separately as a cache, although ports with different rates can be used, it cannot adapt to that kind of multi-channel application, for example, channelized application of a single port

Moreover, it is not possible to arbitrarily allocate the size of the cache between channels or ports as the application environment changes.

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