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Planar arrangement planning method considering voltage reduction

A voltage drop and layout technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of maximum allowable voltage reduction, integrated circuit operating voltage reduction, etc., to achieve the goal of reducing the maximum voltage drop and average voltage drop Effect

Inactive Publication Date: 2006-05-17
FUDAN UNIV
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

With the development of the technology, the function of the integrated circuit is more and more powerful, the current density and the length of the connection are increased, which brings a larger voltage drop
Moreover, the operating voltage of the integrated circuit decreases with the development of the process, so that the maximum allowable voltage drop for normal operation is also reduced.
Therefore, the voltage drop problem will become more and more prominent with the development of the process

Method used

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  • Planar arrangement planning method considering voltage reduction
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  • Planar arrangement planning method considering voltage reduction

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Experimental program
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Effect test

specific Embodiment approach

[0017] (1) Construct an initial layout and represent it with corresponding data structures such as B*-tree[9], O-tree[10], Sequence pair[11], etc.

[0018] (2) The objective function in the simulated annealing algorithm is as follows:

[0019] Cost = αAera + βCost 1R , where 0≤α, β≤1 and α+β=1, Aera is the area of ​​the layout, and Cost IR is the voltage drop objective function value of the layout. cost IR The expression for is as follows:

[0020] Cost IR = Σ i = 1 i = N w i ( d max - d i ) , Among them, d max is the longest distance from the point of maximum voltage drop, d i for module b i Distance from th...

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Abstract

A planning method of plane layout considering voltage drop in auxiliary design of computer applying integrated circuit includes setting up a quick and quantization voltage drop model, applying special selection policy in simulation ¿C annealing course to decrease maximum voltage drop at a layout and average voltage drop effectively.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and specifically relates to a planar layout planning method of large-scale integrated circuits considering voltage drop (IR-drop). technical background [0002] With the development of integrated circuit technology, the working voltage decreases and the power consumption density increases, the problem of voltage drop in the power supply network will become more and more prominent. The voltage drop is caused by the current passing through the resistance on the power network. With the development of the technology, the function of the integrated circuit becomes more and more powerful, and the current density and the length of the connection increase accordingly, which brings a greater voltage drop. Moreover, the operating voltage of the integrated circuit decreases with the development of the process, so that the maximum allowable voltage drop for normal operat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 陈建赵长虹周晓方周电
Owner FUDAN UNIV