Device and method for controlling high-level data link

A data link control and high-level technology, applied in the field of data communication, can solve the problems of high CPU operation load and low processing efficiency, and achieve the effect of reducing CPU operation load, improving transmission processing efficiency, and realizing pipeline operations.

Active Publication Date: 2007-06-20
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The technical problem to be solved by the present invention is to provide a new device and method for realizing high-level data link con

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  • Device and method for controlling high-level data link
  • Device and method for controlling high-level data link
  • Device and method for controlling high-level data link

Examples

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Embodiment Construction

[0039]As shown in FIG. 4 , in one embodiment of the present invention, the device for implementing high-level data link control (HDLC module for short) includes an HDLC processing channel (Hdlc_Channel) 44 and a bus interface module (Ahb_Master) 46 . The HDLC processing channel 44 is connected to the peripherals through the bus interface module 46 via an Advanced High-performance Bus (AHB), so as to interact with the peripherals. The HDLC processing channel 44 is used to implement DMA data transfer function and HDLC physical layer basic processing, such as initiating DMA request, realizing data transfer from source peripheral to HDLC module, HDLC basic processing flow, and realizing data transfer from HDLC module to destination peripheral. The bus interface module 46 is connected to an advanced high-performance bus, and is used to provide a service data entry and exit channel of the HDLC protocol, wherein the data input before the downlink HDLC processing or the data output aft...

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Abstract

This invention relates to a kind of device of realizing high-level data link control. It includes: bus interface module that has outer interactive function through advanced high-performance bus, HDLC processing lane that connects with stated bus interface module. The stated HDLC processing lane includes core processing module and core control module, the stated core control module controls core processing module according to peripherals DMA request and reads data form peripherals to have HDLC processing through bus interface module. After the completion of core processing module handle, it informs related peripherals or CPU to read the completed data. This invention also provides a corresponding high-level data link control method. Through the providing DMA data movement function in the HDLC processing of this invention, it reduces CPU load and saves CPU processing resource.

Description

technical field [0001] The present invention relates to the field of data communication, and more specifically, relates to a device and method for realizing high-level data link control. Background technique [0002] HDLC (High-Level Data Link Control, high-level data link control) is a bit-oriented data link control protocol. Since the transmission control function and processing function of the HDLC protocol are separated, and it has the characteristics of transparent transmission, high reliability, high transmission efficiency, and high flexibility, it has been widely used in the field of data communication and is an important technology to ensure reliable interoperability of data information. [0003] As shown in Figure 1, a complete HDLC frame consists of a flag sequence F, an address field A, a control field C, an information field I and a frame check sequence field FCS. Wherein the bit combination 01111110 is specified as the frame flag sequence in the HDLC frame, al...

Claims

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Application Information

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IPC IPC(8): H04L29/08
Inventor 陈东斌吴奇祥
Owner HUAWEI TECH CO LTD
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