110 results about "High-Level Data Link Control" patented technology

The present disclosure provides systems and methods for rapid circuit provisioning in Optical Transport Networks (OTN) using signaling and routing protocols thereby enabling fast mesh restoration. The present invention utilizes a shim layer between OTN messaging (e.g., GCC or High-Level Data Link Control (HDLC)) and the associated signaling and routing protocol (e.g., OSRP, GMPLS, etc.). If an ODUk Connection CTP or TTP needs to be created, the shim layer runs a fast “OTN Setup” protocol, while buffering out going OTN messages. Incoming messages are still processed and do not require additional buffering. The purpose of the OTN Setup protocol is to allow the OTUk to re-frame on its client ODUk, while buffering out-going messages. When re-framing completes, buffers are released and the OTN messaging resumes without dropping any of the signaling frames.

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.