Manufacturing method of semiconductor device and semiconductor device

a manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of short channel characteristics deteriorating junction leakage going up, etc., to improve the performance of the first mos transistor, suppress the increase of junction leakage, and improve the electric resistance of the source/drain region

Inactive Publication Date: 2008-10-23
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach reduces junction leak, minimizes the rise in electric resistance, and improves the performance of MOS transistors by preventing silicide cohesion and maintaining the integrity of the gate electrode's electrical properties during heat treatment.

Problems solved by technology

Furthermore, by the generation of cohesion, the silicide in the source / drain region may break through the pn junction surface formed in the boundary of the silicon substrate and the source / drain region, it may become a configuration over both the silicon substrate and the source / drain region, and junction leak may increase.
On the other hand, in performing the silicidation of a source / drain region and a gate electrode simultaneously unlike a described method, usually, since the thickness of the gate electrode is very larger than the junction depth of the source / drain region, when all the regions of the gate electrode are silicided, the silicide layer in the source / drain region becomes deep too much, junction leak will go up or short channel characteristics will deteriorate.

Method used

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  • Manufacturing method of semiconductor device and semiconductor device
  • Manufacturing method of semiconductor device and semiconductor device
  • Manufacturing method of semiconductor device and semiconductor device

Examples

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embodiment 1

[0048]FIG. 1 is a cross-sectional view showing the structure of the semiconductor device concerning Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor device concerning Embodiment 1 is provided with the nMOS region in which nMOS transistor 5 is formed, and the pMOS region in which pMOS transistor 15 is formed. In the semiconductor device concerning Embodiment 1, semiconductor substrate 1 which is a p type silicon substrate, for example is formed. In the upper surface of semiconductor substrate 1 in the boundary of the nMOS region and the pMOS region, element isolation insulating film 2 which includes a silicon oxide film, for example is formed, and nMOS transistor 5 and pMOS transistor 15 are electrically separated by the element isolation insulating film 2 concerned. Element isolation insulating film 2 concerning Embodiment 1 is formed by the trench isolation method.

[0049]P type well region 3 is formed in the upper surface of semiconductor substrate 1 in a...

embodiment 2

[0086]FIG. 28 is a cross-sectional view showing the structure of the semiconductor device concerning Embodiment 2 of the present invention. Although silicide layers 7 and 17 were formed in the upper surface of semiconductor substrate 1 in the semiconductor device concerning above-mentioned Embodiment 1, silicide layers 7 and 17 are formed on the upper surface of semiconductor substrate 1 in the semiconductor device concerning Embodiment 2. Therefore, the upper surface of silicide layer 7 is located up rather than the upper surface of the portion on which gate insulating film 8 is formed in semiconductor substrate 1, and the upper surface of silicide layer 17 is located up rather than the upper surface of the portion on which gate insulating film 18 is formed in semiconductor substrate 1. Concretely, the upper surface of silicide layers 7 and 17 is located in the 5 nm or more upper part, respectively rather than the upper surface of the portion on which gate insulating films 8 and 18...

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Abstract

The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered.A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source / drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source / drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source / drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source / drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source / drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a division of and claims the benefit of priority under 35 U.S.C. §120 from U.S. application Ser. No. 11 / 381,654, filed May 4, 2006, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2005-197055 filed on Jul. 6, 2005, the entire contents of which are incorporated hereby by reference.[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device provided with a MOS transistor in which all the regions of the gate electrode are silicided, and its manufacturing method.[0004]2. Description of the Background Art[0005]In the CMOS device represented by system-on-chip, densification and microfabrication are advanced every year, and the gate length of the MOS transistor is set to 0.1 μm or less, and has reached to tens of nm. On the other hand, thickness reduction of the gate insulating film of a MOS transistor is also advanced, and this thickness reduction t...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/78
CPCH01L21/28097H01L21/28518H01L21/823814H01L21/823835H01L21/82385H01L29/4975H01L29/66545H01L29/6659H01L29/7833H01L21/18H01L21/8228
InventorKOMORI, SHIGEKI
OwnerRENESAS TECH CORP