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Plating method

Inactive Publication Date: 2011-12-29
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In such cases, plating is more easily formed in the vicinity of the cathode electrode than in the other portion, which makes it difficult to uniformly form the plating in a plane of the semiconductor wafer (Refer to Japanese Patent Application Laid-Open (JP-A) No. 2008-25000).

Method used

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  • Plating method
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Experimental program
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first embodiment

(First Embodiment)

[0031]As shown in FIG. 4, dummy post-formation areas 140 identical to the post-formation areas 121 the product area 130 in shape are disposed between the electrode pins 70 and the post-formation areas 121 of the product area 130, and plating is carried out to respectively form posts both in the post-formation areas 121 of the product area 130 and in the dummy post-formation areas 140. Although posts formed in the dummy post-formation areas 140 are enlarged, it is possible to prevent or suppress enlargement of the posts formed in the post-formation areas 121 of the product area 130.

second embodiment

(Second Embodiment)

[0032]When the dummy post-formation areas 140 according to the first embodiment cannot be disposed due to the distance in the layout over the whole wafer or a size of the dummy posts, rectangular dumpy post-formation areas 142 which can be disposed in a shorter distance is disposed between the electrode pins 70 and the post-formation areas 121 in the product area 130. Even in this case, the posts formed in the dummy post-formation areas 142 are also enlarged, however, it is possible to prevent or suppress enlargement of the posts formed in the post-formation areas 121 in the product area 130.

third embodiment

(Third Embodiment)

[0033]In the disposition of the dummy post-formation areas 140 according to the first embodiment, and of the dummy post-formation areas 142 according to the second embodiment, plural dummy post-formation areas are discretely disposed in the dummy post-formation areas 140 and the dummy post-formation areas 142, thus, there are intervals between the dummy post-formation areas 140 and between the dummy post-formation areas 142. With the intervals, a possibility, even a little, remains to influence the posts formed in the post-formation areas 121 of the product area 130.

[0034]Therefore, according to the present embodiment, the dummy post-formation areas 144 disposed between the electrode pins 70 and the post-formation areas 121 in the product area 130 are made to be in a continuous shape surrounding points where the electrode pins 70 contact, thus, it is possible to prevent enlargement of the posts formed in the post-formation areas 121 in the product area 130 by the i...

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PUM

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Abstract

Disclosed is a plating method including: performing plating on a plating surface of a plating substrate with a cathode electrode contacting an area in an outer circumferential section of the plating substrate where the cathode electrode is to be contacted, the plating substrate being provided with a dummy plating area between the area where the cathode electrode is to be contacted and a product area on the plating surface of the plating substrate, by supplying a plating solution to the plating surface of the plating substrate and applying electric current between the cathode electrode and an anode electrode via the plating solution.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority under 35 USC 119 from Japanese Patent Application No. 2010-142852 filed on Jun. 23, 2010, the disclosure of which is incorporated by reference herein.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to a plating method, and more particularly, to a plating method for plating on a semiconductor wafer.[0004]2. Related Art[0005]For plating on a semiconductor wafer, there may be cases in which an anode electrode is disposed so as to face a plating surface of the semiconductor wafer and a cathode electrode is brought into contact with an outer circumference portion of the semiconductor wafer. In such cases, plating is more easily formed in the vicinity of the cathode electrode than in the other portion, which makes it difficult to uniformly form the plating in a plane of the semiconductor wafer (Refer to Japanese Patent Application Laid-Open (JP-A) No. 2008-25000).[0006]A major object ...

Claims

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Application Information

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IPC IPC(8): C25D5/02
CPCC25D5/02C25D5/08C25D17/001C25D17/10C25D7/12C25D7/123
Inventor SAITO, HIROKAZUSAMESHIMA, HIDEYUKI
Owner LAPIS SEMICON CO LTD