Delay adjustment device, semiconductor device and delay adjustment method

a delay adjustment and semiconductor technology, applied in the direction of information storage, static storage, digital storage, etc., can solve the problems of increasing circuit size, increasing circuit size, and difficulty for requestors to determine the timing of data retrieval, so as to reduce chip size and reduce cost

Inactive Publication Date: 2012-06-28
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This solution downsizes the circuit for flight time adjustment, reducing chip size and cost, while enabling reliable data retrieval synchronized with the internal clock signal, and allowing for fine-tuned timing adjustments during operation without power restarts.

Problems solved by technology

This makes it difficult for the requestor to determine the timing to retrieve data.
The circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-276396 requires a circuit to preliminarily write a calibration pattern to a memory, and a comparison circuit to compare data read from a memory, resulting in an increase in circuit size.
In these cases, the control circuits use a FIFO, for example, which results in an increase in circuit size.
The present inventor has found a problem that the size of a circuit for adjusting the flight time is increased.

Method used

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  • Delay adjustment device, semiconductor device and delay adjustment method
  • Delay adjustment device, semiconductor device and delay adjustment method
  • Delay adjustment device, semiconductor device and delay adjustment method

Examples

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first exemplary embodiment

[0031]FIG. 1 is a block diagram showing an example of a configuration of a delay adjustment device (delay adjustment circuit) according to the first exemplary embodiment of the present invention. A delay adjustment circuit 1 includes a data retrieve unit 10 and a control unit 20.

[0032]The data retrieve unit 10 receives the data signal and data strobe signal from the DDR SDRAM, and outputs the data value of the data signal in accordance with the data strobe signal. The control unit 20 controls the timing for the data retrieve unit 10 to output the data value. Specifically, the data retrieve unit 10 is controlled such that the control unit 20 adjusts a valid period of the data strobe signal.

[0033]The control unit 20 calculates the flight time using the data strobe signal. Specifically, the control unit 20 issues the read command to the DDR SDRAM, and retrieves the value of the data strobe signal (hereinafter also referred to as “strobe value”). The control unit 20 then calculates the ...

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Abstract

A semiconductor device including an adjustment mode and a normal operation mode, including a first terminal to be coupled to the memory and configured to output a read command to the memory in the adjustment mode and not to output a write command in the adjustment mode, and a second terminal to be coupled to the memory and configured to receive a data strobe signal from the memory in the adjustment mode and not to output a signal to the memory in the adjustment mode.

Description

[0001]The present application is a Continuation Application of U.S. patent application Ser. No. 12 / 588,909 filed on Nov. 2, 2009, which is based on Japanese Patent Application No. 2008-295065, Filed on Nov. 19, 2008, the entire contents of which is incorporated herein by reference.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to delay adjustment between a memory and a memory controller, and particularly to delay adjustment between a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) and a memory controller.[0004]2. Description of Related Art[0005]A DDR SDRAM is a memory including a high-speed transfer function. In particular, the DDR SDRAM can read and write data on both the rising and falling edges of the clock signal for synchronization between circuits. That is to say, the DDR SDRAM inputs and outputs data with twice the frequency of an external clock. Therefore, the DDR SDRAM has a narrower data width (width of determined data), ...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C7/00
CPCG11C7/1066G11C7/22G11C7/222G11C7/225G11C29/02G11C2207/2254G11C11/4076G11C11/407
InventorONISHI, SATOSHI
OwnerRENESAS ELECTRONICS CORP