Dual metal fill and dual threshold voltage for replacement gate metal devices

a metal device and threshold voltage technology, applied in the field of semiconductor devices, can solve the problems of inacceptable yield and device variability, high complexity and cost of fabrication, and high cost of manufacturing

Inactive Publication Date: 2014-03-27
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method for making two transistors with different threshold voltages. The process involves creating two gate cavities, depositing a layer of gate dielectric, metals for the workfunction and a titanium layer, and a hardmask layer. In one embodiment, a second fill metal is then deposited to fill the gate cavity of the second transistor. In another embodiment, a second titanium layer and hardmask layer are removed and replaced with a second fill metal to further fill the gate cavity of the second transistor. The transistors are then planarized. This method allows for more precise placement of the workfunction metals and provides better control over the threshold voltage of the transistors.

Problems solved by technology

However, this technique often requires additional mask levels, resulting in higher complexity and cost for fabrication.
Furthermore, residual work function metals on respective devices may cause unacceptable levels of yield and device variability.

Method used

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  • Dual metal fill and dual threshold voltage for replacement gate metal devices
  • Dual metal fill and dual threshold voltage for replacement gate metal devices
  • Dual metal fill and dual threshold voltage for replacement gate metal devices

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Embodiment Construction

[0026]FIG. 1 shows a semiconductor structure at a starting point for fabrication of an embodiment of the present invention. A silicon layer 102 forms the bottom of the structure. Disposed on silicon layer 102 is dielectric layer 110. A first gate cavity 106 and second gate cavity 104 are formed within the dielectric layer 110. Spacers 108 form the interior walls of the gate cavity 104 and gate cavity 106. The spacers 108 may be comprised of nitride.

[0027]FIG. 2 shows a semiconductor structure 200 at a subsequent point in the fabrication process where gate dielectric film 212 is deposited in the first gate cavity 206 and second gate cavity 204. Most any suitable gate dielectric material can be used. In one embodiment, the gate dielectric film comprises one of hafnium oxide, silicon oxide, or a compound of the form HfSiOx. As stated previously, similar elements may be referred to by similar numbers in various figures of the drawing, in which case typically the last two significant dig...

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Abstract

A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to semiconductor devices and more particularly to integrated circuits including metal gate MOS transistor devices and fabrication methods for making the same.BACKGROUND OF THE INVENTION[0002]Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/49H01L27/088
CPCH01L27/088H01L29/49H01L21/82345H01L21/823842H01L21/28088H01L29/66545
InventorBERLINER, NATHANIELDEMAREST, JAMES JOHNEDGE, LISA F.HARAN, BALASUBRAMANIAN S.
OwnerAPPLIED MATERIALS INC