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Cache memory and operation method thereof

Active Publication Date: 2017-09-07
ELECTRONICS & TELECOMM RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is about a type of cache memory that helps maintain data consistency and enhances access speed. The patent describes a method for using this cache memory. The technical effect of this invention is improved performance and efficiency in accessing data from cache memory.

Problems solved by technology

In this case, an issue may occur from the coherence on data stored in different level-1 cache memories.

Method used

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  • Cache memory and operation method thereof
  • Cache memory and operation method thereof
  • Cache memory and operation method thereof

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Embodiment Construction

[0033]Hereinafter, embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings. In the description below, details such as detailed configurations and structures are simply provided to help overall understanding. Therefore, without departing from the technical idea and scope of the inventive concept, modifications on embodiments described in this specification may be performed by those skilled in the art. Furthermore, description of well-known functions and structures are omitted for clarity and conciseness. The terms used herein are defined in consideration of functions of the inventive concept and are not limited to specific functions. The definition of terms may be determined based on the details in description.

[0034]Modules in drawings or detailed description below may be shown in the drawings or may be connected to another component other than components described in detailed description. Each of connections between modules o...

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Abstract

Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2016-0025201, filed on Mar. 2, 2016, the entire contents of which are hereby incorporated by reference.BACKGROUND[0002]The present disclosure relates to cache memory, and more particularly, to cache memory and an operation method thereof.[0003]Cache memory is high-speed memory disposed between a processor and system memory in order to compensate an operating speed between the processor and the system memory (for example, SDRAM). The cache memory may temporarily store instructions or data requested from the processor.[0004]In general, cache memory may include level-1 cache memory and level-2 cache memory. The level-1 cache memory may be directly connected to a processor and provide fast access. The level-2 cache memory may be positioned in a lower level of the level-1 cache memory and transmit / receive data to / from the level...

Claims

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Application Information

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IPC IPC(8): G06F12/0811G06F12/0842G06F12/0875G06F12/084
CPCG06F12/0811G06F12/084G06F2212/62G06F12/0875G06F2212/6042G06F12/0842Y02D10/00
Inventor HAN, JIN HOKWON, YOUNG-SUBYUN, KYUNG JINEUM, NAK WOONG
Owner ELECTRONICS & TELECOMM RES INST