Interleaver memory access apparatus and method of CDMA system

a memory access and interleaver technology, applied in the field of cdma system, can solve the problems of low power consumption, disturbance of rapid data processing, unexpected data loss (an error), etc., and achieve the effects of improving addressing and access operation, reducing power consumption, and increasing data access speed

Inactive Publication Date: 2005-11-15
LG ELECTRONICS INC
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0030]Therefore, an object of the present invention is to provide an access apparatus of an interleaver memory that is capable of reducing a p

Problems solved by technology

However, when a data is transmitted through the radio interface, a data loss (an error) may unexpectedly occur due to various noise.
In this respect, however, in order to read and write the code symbols of one frame, the serial data, since the address (the row and the column) generation and the access operation of the interleaver memory should be performed so frequently, causing a disturbance to the rapid data processin

Method used

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  • Interleaver memory access apparatus and method of CDMA system
  • Interleaver memory access apparatus and method of CDMA system
  • Interleaver memory access apparatus and method of CDMA system

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Embodiment Construction

[0046]Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0047]FIG. 6 is a schematic block diagram of an interleaver memory access apparatus of a CDMA system in accordance with the present invention.

[0048]As shown in the drawing, the interleaver memory access apparatus of a CDMA system of the present invention includes an interleave memory 100, a shift register unit 101 for simultaneously receiving 18 bit code symbols from the interleaver memory and outputting it by 6 code symbols; an index decoding unit 102 for decoding the 6 code symbols outputted from the shift register unit and generates a Walsh index; an orthogonal modulator for outputting 64 Walsh codes on the basis of the Walsh index outputted from the index decoding unit; and an address generator and control logic for controlling the access operation of the interleaver memory and the input and output operation of the shift...

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Abstract

An interleaver memory access apparatus of a CDMA system including an interleaver memory for storing code symbols to be transmitted; a shift register unit for simultaneously receiving 18 bit code symbols from the interleaver memory and outputting the 18 bit code symbols in three sets of 6 bit code symbols; an index decoding unit for decoding the 6 bit code symbols outputted from the shift register unit and generates a Walsh bit index; an address generator and control logic for controlling an access operation of the interleaver memory and the input and output operation of the shift register unit and the index coding unit; and an orthogonal modulator for outputting 64 bit Walsh codes based on the Walsh bit index outputted from the index decoding unit.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a CDMA system, and more particularly to an interleaver memory access apparatus and method of a CDMA system.[0003]2. Description of the Background Art[0004]FIG. 1 is a schematic block diagram of a general CDMA system in accordance with a conventional art. As shown in the drawing, the conventional CDMA system includes a frame quality indicator 10 for attaching a frame quality indicator indicating a data rate to a source data, a trail bit attaching unit 20 for attaching a 8 bit encoder trail bit to an output of the frame quality indicator 10, a convolutional encoder 30 for receiving the data bit from the trail bit attaching unit 20 and generating three code symbols (a serial data) per each data bit, a code symbol repeating unit 40 for repeating a symbol for the convolutional encoder 30 to make the same data size as the full rate, an interleaver memory 50 for storing the code symbols outputt...

Claims

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Application Information

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IPC IPC(8): H04J11/00H03M13/27H03M13/35H04J13/00
CPCH04J13/0048H04J13/12H03M13/27H04J13/18
Inventor KIM, DAE SIK
Owner LG ELECTRONICS INC
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