Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same

Abstract

A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 10-2007-0045946 filed on May 11, 2007, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a strip level substrate and method for manufacturing a semiconductor package using the same capable of minimizing an early warpage phenomenon of a strip level substrate.[0003]A sheet of wafer is provided with several hundred or several thousand chips on which the same electrical circuits are printed. However, the printed chips cannot transfer or receive external electrical signals, and further, the chips having fine circuits are easily damaged by external shocks. Therefore, there is a need for a semiconductor package in which the chips are electrically connected, more resistant to external shocks, and ...

AI Technical Summary

Benefits of technology

This approach effectively reduces the warpage phenomenon, enhancing the integrity and reliability of semiconductor packages by minimizing faulty operations and defects during the manufacturing process.

Problems solved by technology

However, the printed chips cannot transfer or receive external electrical signals, and further, the chips having fine circuits are easily damaged by external shocks.

However, although the facile nature of the process is advantageous, during the process for manufacturing the package, the solder resist applied on the front surface of the strip level substrate repeatedly expands and contracts during the reflow process, causing an early warpage phenomenon on the strip level substrate.

As a result, the progress of the process thereafter becomes more difficult and the unit level semiconductor package degrades.

Such a problem also occurs in a flip chip package during the manufacture of a semiconductor package by applying a solder resist on the electrode terminal of a strip level substrate, progressing the reflow and then forming a bump.

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