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Rendering processor

a processing processor and image technology, applied in the direction of processing architecture/configuration, instruments, digital computers, etc., can solve the problems of high hardware processing load, complex output order of rendering results, and high cost, and achieve the effect of simple method

Inactive Publication Date: 2014-01-21
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the conventional method, however, the arrangement for outputting graphics in a correct order by controlling the rendering command processing timing and the rendering result output order is complex, and the cost thereof is high.
For this reason, the processing load of hardware is heavy.
The memory cost for it is high.
However, the time needed to render the band image changes depending on the degree of complexity.
Furthermore, since the process is performed for each band image, the memory cost is slightly lower than that when holding data of one frame.
Instead, process assignment to the band images and the order control are more complex than that when processing each frame.

Method used

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first embodiment

[0016]An example of the arrangement of a rendering processor 100 according to this embodiment will be described first with reference to the block diagram of FIG. 1. As shown in FIG. 1, the rendering processor 100 includes a main processor 102, a sub-processor 103 that processes information output from the main processor 102, and a sub-processor 104 that processes information output from the sub-processor 103. The main processor 102 and the sub-processors 103 and 104 are connected in series in the order named to execute pipeline processing. Each of the main processor 102 and the sub-processors 103 and 104 includes a plurality of units, as described in detail below.

[0017]First, the main processor 102 will be explained. The main processor acquisition unit 102A receives a rendering command 101 of a rendering target image, which is described in a graphic language such as the vector graphics language. Using the rendering command 101, the main processor collection unit 102B collects the ed...

second embodiment

[0042]In the first embodiment, the operation of the rendering processor 100 including the two sub-processors connected in series after the main processor 102 has been described. In the second embodiment, a rendering processor including a main processor, a first sub-processor that processes information output from the main processor, and an (i+1)th (i=1, 2, . . . , N−1) sub-processor that processes information output from an ith sub-processor will be described.

[0043]In this case, the main processor acquires the rendering command of a rendering target image and collects the edge information and color information of the pixels of the rendering target image using the rendering command, as in the first embodiment. The rendering target image is segmented into N rectangular regions in the vertical line direction. The segmented rectangular regions will be defined as a first rectangular region, a second rectangular region, . . . , and an Nth rectangular region from right to left. In this cas...

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Abstract

A main processor collects the edge information and color information of the pixels of a rendering target image using a rendering command, and sends the collected edge information and color information of the pixels to a sub-processor of the succeeding stage. The sub-processor sends the edge information and color information of a left rectangular region to a sub-processor, and also renders a right rectangular region and, upon receiving a process wait signal from the sub-processor, sends the rendering result to the sub-processor. The sub-processor renders the left rectangular region and sends the rendering result to the outside, and also sends, to the outside, the rendering result of the right rectangular region acquired by sending a process wait signal to the sub-processor.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an image rendering technique.[0003]2. Description of the Related Art[0004]Patent references 1 (Japanese Patent No. 03809284) and 2 (Japanese Patent Laid-Open No. 09-167243) disclose methods of causing renderers that process rendering commands described in the vector graphics language to parallelly process the rendering commands for the purpose of speeding up the process or distributing the load. Patent reference 1 discloses a method of transferring rendering commands to renderers via a common bus and causing the renderers to parallelly process images. Patent reference 2 discloses a method of dividing a rendering region into bands and parallelly processing the bands.[0005]As the resolution of graphics rises, a technique of parallelly processing rendering commands is used. In the conventional method, however, the arrangement for outputting graphics in a correct order by controlling the ren...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06T1/20G06F15/16
CPCG06T1/20G06F2209/5017G06F9/5011
Inventor IGUCHI, MASAYUKI
Owner CANON KK