3results about How to "Clear logical structure" patented technology

The invention relates to the field of artificial intelligence, and provides a presentation file automatic generation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: calling a first model interface, and introducing presentation file outline information or presentation file theme information and typesetting prompt information to obtain a first return result; generating a paging prompt content sequence according to the first return result; the target theme style and the paging prompt content sequence are input into a pre-trained presentation file typesetting design model, a paging typesetting design description sequence is obtained, the paging typesetting design description sequence comprises a plurality of typesetting pages, and one typesetting page corresponds to one typesetting design description; and generating a target presentation file based on the paging typesetting design description sequence and the target theme style, and outputting the target presentation file. The PPT generated by the method is more compact in structure and better in logicality, and the PPT typesetting design has better novelty and uniqueness, so that the personalized requirements of users can be better met.

The invention relates to the technical field of data processing and exchange forwarding, and provides a normalized splicing method of a frame header and a load, which is suitable for a multi-interconnection protocol frame generation process, and a multi-interconnection protocol frame generation device based on an FPGA (Field Programmable Gate Array). According to the method, generated frame header data is processed beat by beat, and the last beat of the frame header and the first beat of the load are simultaneously generated in the same beat through a set synchronous control signal, so that the frame header and the load are spliced in a seamless connection manner to form a complete data frame; and the frame header and the load in the splicing module are input in a whole-beat segmented manner. According to the splicing method provided by the invention, the requirement of generating data frames of different protocol types can be met, the complexity of a heterogeneous protocol frame generation process is remarkably reduced, the hardware resource utilization rate is improved by more than or equal to N times, the cost and power consumption advantages of the environment are enhanced, and meanwhile, new type protocol expansion can be flexibly carried out on the environment.

A high-precision timing method of a semi-physical simulation system, steps are as follows: (1) creating an overflow linked list and a ready linked list; (2) a user inputs information of a timer to be created; (3) judging whether a time length corresponding to a remaining tick number in target timer information is greater than a preset remaining time threshold; if the time length corresponding to the remaining tick number is greater than the preset remaining time threshold, performing an overflow linked list updating operation, completing creation of a polling timer and updating of the overflow linked list; otherwise, performing a ready linked list updating operation, completing creation of a ready timer and updating of the ready linked list; (4) when an overflow of the ready timer occurs, performing task execution and updating operations on each node in the ready linked list in sequence; (5) when an overflow of the polling timer occurs, performing information updating and registration operations on each node in the overflow linked list in sequence; (6) repeating steps (2)-(5) until the user no longer inputs timer information.