Method and system for automatic schedule logic simulation and code coverage rate analysis

Abstract

The invention includes following steps: (1) using main module pre-compiles logic to be tested in order to generate pre-compiled file suitable to analysis for percentage of coverage of code; (2) the main module dispatches all cases for emulation provided by users to create a index catalog of cases for emulation; (3) based on the said catalog the main module executes each case for emulation to carry out emulation test for logic to be tested; (4) based on pre-compiled file, the main module obtains and saves the result of percentage of coverage of code after executing each case for emulation. The invention can realize automatic emulation and analysis in full working flow.

Description

technical field [0001] The invention relates to the field of system simulation, in particular to a method and system for automatic scheduling logic simulation and code coverage analysis. Background technique [0002] In large-scale logic (FPGA / ASIC) verification, simulation and code coverage analysis is one of the important processes. [0003] Its basic execution process is as follows: [0004] (1) Precompilation (Instrumentation) - integrate the logic under test to generate files suitable for code coverage analysis; [0005] (2) Simulation—the execution process of the simulation use case, adding code coverage analysis in the process; [0006] (3) Code coverage result analysis (Reporting)—combine multiple simulation use cases to generate code coverage data and generate a code coverage report. [0007] Typically, each logic project verification will require the support of multiple simulation use cases. There are many technologies in the industry on how to complete the co-...

AI Technical Summary

Problems solved by technology

[0014] Disadvantage 1: The configuration is performed temporarily during test execution, and its effect depends entirely on the personal experience and technical level of the executor;

[0015] Disadvantage 2: It is difficult to unify the implementation process, it is not easy to accumulate and share good experience, and it is not easy to form a standardized operation process;

[0016] Disadvantage 3: Every test execution requires manual participation, and logic verifiers cannot be freed from these mechanically repetitive transactions

Although each simulation use case can be automatically executed through scripts, the work of starting each simulation use case requires the manual participation of logic verifiers

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