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Memory part, its making method and operation method

A technology of operation method and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as difficult process integration

Active Publication Date: 2009-02-25
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, this EEPROM needs to form a floating gate and a control gate, which is difficult to integrate with the general CMOS process, and an additional silicon oxide layer has to be provided to isolate the floating gate and the bit line.

Method used

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  • Memory part, its making method and operation method
  • Memory part, its making method and operation method
  • Memory part, its making method and operation method

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Embodiment Construction

[0085] Figure 2A is a schematic cross-sectional view showing a memory device according to an embodiment of the present invention. Please refer to Figure 2A , the memory element of this embodiment is composed of, for example, a substrate 200 , a plurality of conductive layers 210 , a composite dielectric layer 220 and a plurality of gates 230 . Wherein, the conductor layer 210 is disposed on the base 200 . The composite dielectric layer 220 is disposed on the substrate 200 and covers the conductor layer 210 . The gate 230 is, for example, disposed on the composite dielectric layer 220 across the conductor layer 210 .

[0086] Wherein, the substrate 200 is, for example, a P-type silicon substrate. The material of the conductive layer 210 is, for example, doped polysilicon, and the dopants in the doped polysilicon are, for example, N-type dopants such as arsenic or phosphorus. The dopant, for example, diffuses downward from the conductive layer 210 to the substrate 200 , s...

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Abstract

A memory element comprises a base, a plurality of conductor layers, a compound dielectric layer and a plurality of gates, wherein a plurality of the conductor layers are equipped on the base; the compound dielectric layer is equipped on the base to cover the conductor layers, and the compound dielectric layer comprises a charge trapping layer; the gates are equipped on the compound dielectric layer and cross the conductor layers, wherein the conductor layers can serve as the local site lines to reduce the resistance and improve the efficiency of the memory element.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method and operating method, and in particular to a memory element and its manufacturing method and operating method. Background technique [0002] The non-volatile memory in the memory element is a memory in which the data stored in it will not disappear due to power supply interruption. It has non-volatile memory that can perform multiple data programming, reading, erasing, etc. Memory, such as electrically erasable programmable read only memory (EEPROM), silicon nitride read only memory (NROM), etc., has been widely used in various personal computers and electronic devices. [0003] Figure 1A A top view of a known silicon nitride read only memory is shown. Figure 1B for along Figure 1A A schematic cross-sectional view of the line I-I'. Please refer to Figure 1A and Figure 1B In this silicon nitride read-only memory, a plurality of gate structures 125 are first for...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L23/522H01L21/8247H01L21/768
Inventor 刘承杰熊黛良
Owner MACRONIX INT CO LTD