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Divider circuit

A technology of circuit and division, applied in the direction of electric digital data processing, using non-contact manufacturing equipment for calculation, instruments, etc., can solve the problem of increasing the processing time of the quotient

Inactive Publication Date: 2010-06-02
SANYO ELECTRIC CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In this way, since the quotient can only be obtained bit by bit in the case of the addition method and the subtraction method, as the number of digits necessary for the quotient increases, the processing time for obtaining the quotient increases.

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Embodiment Construction

[0015] figure 1 It is a figure which shows the structure of the division circuit which concerns on one Embodiment of this invention. The division circuit is composed of registers 10 to 12 , a multiple divisor generation circuit 13 , pipeline registers 14 and 15 , and a quotient generation circuit 16 . In addition, the division circuit of this embodiment is comprised as a part of processors, such as a CPU (Central Processing Unit).

[0016] Registers 10 to 12 are storage areas for storing a dividend, a divisor, and a quotient in division, respectively. These registers 10 to 12 are, for example, accumulators, general-purpose registers, special registers, etc. included in the processor.

[0017] The multiple divisor generating circuit 13 generates a multiple divisor, that is, a number that is an integer multiple of the divisor stored in the register 11 . If the quotient is obtained by every m (integers above 2) bits in the division circuit, then in the multiple divisor generat...

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Abstract

A divider circuit for dividing a dividend by a divisor, includes: a multiplicative divisor generating circuit configured to generate 2m-2 multiplicative divisors that are 2 to 2m-1 times the divisor,the m indicating an integer of 2 or more; and a quotient generating circuit configured to sequentially generate a quotient of the dividend, by m bits in decreasing order of significance, by subtracting from the dividend the divisor and the 2m-2 multiplicative divisors, respectively.

Description

technical field [0001] The invention relates to a division circuit. Background technique [0002] As a method of performing binary division by a processor, generally, addition and return (加え戻し) and subtraction and subtraction (引き凉し) are used. In the case of the addition method and the subtraction method, the divisors are sequentially subtracted from the upper digit of the dividend, and the quotient is obtained bit by bit from the result of the subtraction (for example, Patent Document 1). [0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 10-161854 [0004] Thus, since the quotient can only be obtained bit by bit in the case of the addition method and the subtraction method, the processing time for obtaining the quotient increases as the number of digits required for the quotient increases. Contents of the invention [0005] The present invention has been made in view of the above problems, and an object of the present invention is to pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/52
CPCG06F7/537G06F2207/5353
Inventor 本田岩
Owner SANYO ELECTRIC CO LTD