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Method for eliminating alternate word line bridging

A word line and bridging technology is applied in the field of memory array arrangement that can eliminate interlaced word line bridging, and achieves the effect of eliminating the problem of interlaced word line bridging

Inactive Publication Date: 2009-04-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a method for eliminating interlaced word line bridging, which can effectively solve the problem of GC bridging caused by residues after polysilicon etching, and improve the yield of wafers

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  • Method for eliminating alternate word line bridging

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Embodiment Construction

[0011] Based on the above analysis, the root cause of the interlaced word line bridge (bridge) is caused by too much blank space on the edge of the storage array, so we redesigned DT (trench), AA (Active area, active area), GC ( Gate of Conduct (gate) arrangement, the most important thing is that we have added some DT dummy cells (dummy) on the edge of the storage array. The so-called dummy cells are the same as the existing DTs, but they do not have any practical effect. unit.

[0012] The present invention will be described in detail below in conjunction with a specific embodiment. As shown in FIG. 3, the dummy cells 104 are arranged around the memory array, and after the dummy cells 104 are arranged, the distance from the trench 101 of the dummy cells to the gate 102 is ensured. It must be greater than 0.44nm and less than 3.52nm; and the distance from the trench 101 to the active region 103 of SWD (Sub-Word Line Driver, word line driver circuit) is greater than 0.44nm and ...

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Abstract

The invention relates to a method for eliminating bridging of interlacing word lines. A virtual unit is arranged around a memory array to avoid the bridging of the interlacing word lines in the production process of a wafer and to avoid influence on the function of the wafer. The method can help effectively eliminate the bridging of the interlacing word lines and improve the yield of the wafer.

Description

technical field [0001] The invention relates to a method for arranging a storage array, in particular to a method for arranging a storage array capable of eliminating interlaced word line bridges. Background technique [0002] In the 110nm trench (Deep Trench, referred to as DT) dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) technology node (node), there is often a special failure model - interlaced word line bridge ( Interleave Word Line Bridge, referred to as Interleave WL), this failure model is randomly distributed on the edge of the wafer storage array (array edge). [0003] In order to find out the cause of this failure model, we use Electrical Failure Analysis (EFA for short) and Physical Failure Analysis (PFA for short) to analyze this interlaced word line bridge. [0004] According to the results of PFA analysis, interleave WL only occurs in some special areas on the edge of the storage array, and the root cause is the design probl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522H01L27/108H10B12/00
Inventor 王永刚常建光
Owner SEMICON MFG INT (SHANGHAI) CORP