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Test handler, method for loading and manufacturing packaged chips

A technology for testing a processor and mounting a chip, which is used in measurement devices, electronic circuit testing, single semiconductor device testing, etc.

Active Publication Date: 2012-08-15
MIRAE CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as mentioned above, there is a limit to reducing the process time in an environment where the process is complex and inefficient and the frequency of errors is high

Method used

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  • Test handler, method for loading and manufacturing packaged chips
  • Test handler, method for loading and manufacturing packaged chips
  • Test handler, method for loading and manufacturing packaged chips

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0052] Hereinafter, a test handler according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. image 3 is a top view schematically illustrating a test handler according to an embodiment of the present invention. Figure 4A and 4B is a side view schematically illustrating an example of a loading picker. Figure 5 is a perspective view briefly illustrating another example of the loading picker. Image 6 is a top view schematically illustrating the loading unit and the unloading unit. Figures 7A to 7D is a side view briefly illustrating an example of the operation of the loading buffer and the loading picker. Figures 8A to 8D is a side view schematically illustrating another example of the operation of the loading buffer and the loading picker. Figure 9 is a front view schematically illustrating a loading unit, an unloading unit, and a rotating unit. Figure 10 is a diagram briefly illustrating a ...

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PUM

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Abstract

A test handler, a packaged chip loading method, a test tray transferring method, and a packaged chip manufacturing method are provided. The test handler may include a loading unit, a chamber system, an unloading unit, at least one rotating unit and a transferring unit. The loading unit may include a loading buffer disposed to be movable along a moving path formed over a loading position and a loading picker to perform a loading process on the test tray located at the loading position. The chamber system having the packaged chips connected to a hi-fix board and tested. The unloading unit may include an unloading picker to perform an unloading process on the test tray located at an unloading position. The at least one rotating unit may be disposed between the loading unit and the unloading unit to rotate the test tray transferred from the loading unit from a horizontal posture to a vertical posture, and to rotate the test tray transferred from the chamber system from a vertical posture to a horizontal posture. The transferring unit may transfer the test tray. By the structure, the invention reduces the time of loading process and improves the efficiency of the loading process.

Description

technical field [0001] The present invention relates to a test handler for connecting packaged chips to be tested to a testing machine and classifying packaged chips tested by the testing machine by level based on test results. Background technique [0002] A test handler (also referred to as a "test sorter", "test handler", etc.) may be used to perform electrical tests on the packaged chips at the end of the packaging process. [0003] The test handler is a device for connecting packaged chips to be tested to a specific testing machine for testing the packaged chips and classifying the packaged chips tested by the testing machine by level based on test results. [0004] The test handler performs a loading process, a testing process, and an unloading process using a test tray including a plurality of receiving units that can accommodate packaged chips. [0005] In the loading process, packaged chips to be tested are picked up from a customer tray accommodating the packaged ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28H01L21/677H01L21/66H01L21/00B07C5/344
CPCG01R31/2893G01R31/26H01L22/00
Inventor 范熙乐金炅泰
Owner MIRAE CORPORATION