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Method and device for testing memory

A technology of memory testing and memory, which is applied in the field of memory, and can solve problems such as unreliable reading and writing operations of devices, failure to detect hardware and PCB defects and hidden dangers, and failure to detect signal integrity defects, etc.

Active Publication Date: 2012-12-12
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The inventor has found that the prior art has at least the following problems: although the detection method of the above-mentioned memory can detect the peripheral interconnection fault and internal unit fault of the memory, it cannot detect the defects and defects in the hardware and PCB (Print Circuit Board) design. Hidden dangers, that is, most of the common signal integrity defects or hidden dangers cannot be detected, because even if all the internal cells of the memory are normal, the device may not be able to reliably complete each read and write operation due to signal integrity problems

Method used

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  • Method and device for testing memory
  • Method and device for testing memory

Examples

Experimental program
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Embodiment 1

[0025] An embodiment of the present invention provides a memory testing method, such as figure 1 As shown, the method includes:

[0026] 101. Alternately write the first measurement vector value and the inversion value of the first measurement vector value into the memory according to the manner of changing the memory address.

[0027] In this step, the measured vector value and its inversion value are alternately written into the address space to be tested in the memory. The address space to be tested can be but not limited to the entire address space of the memory, and can also be set by the tester according to the specific situation , for example, a part of addresses starting from the lowest address, which is not limited in this embodiment.

[0028] Wherein, the first measurement vector is specifically determined by the tester according to specific test requirements, and the value of the first measurement vector can be selected from a preset default value, or can be input ...

Embodiment 2

[0051] An embodiment of the present invention provides a memory testing method, such as figure 2 As shown, the method includes:

[0052] 201. Alternately write a first measurement vector value and an inversion value of the first measurement vector value into a memory according to a manner of gradually changing memory addresses.

[0053] In this step, the measured vector value and its inversion value are alternately written into the address space to be tested in the memory. The address space to be tested can be but not limited to the entire address space of the memory, and can also be set by the tester according to the specific situation , for example, a part of addresses starting from the lowest address, which is not limited in this embodiment.

[0054] The method of alternately writing the first measurement vector value and the inversion value of the first measurement vector value into the memory includes the following two methods:

[0055] In the first type, the first mea...

Embodiment 3

[0118] An embodiment of the present invention provides a memory testing device, such as Figure 5 As shown, the device includes: a write operation unit 41 and a first detection unit 42 .

[0119] The write operation unit 41 is configured to alternately write the first measurement vector value and the flipped value of the first measurement vector value into the memory according to the sequence of increasing memory addresses.

[0120] In this step, the measured vector value and its inversion value are alternately written into the address space to be tested in the memory. The address space to be tested can be but not limited to the entire address space of the memory, and can also be set by the tester according to the specific situation , for example, a part of addresses starting from the lowest address, which is not limited in this embodiment.

[0121] Wherein, the first measurement vector is specifically determined by the tester according to specific test requirements, and the ...

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Abstract

The invention discloses a method and a device for testing a memory, which relate to the field of storage testing, realize the test of a signal integrity problem and expose hidden troubles of the signal integrity. The method for testing the memory comprises the following steps: writing a first measurement vector value and a flip value of the first measurement vector value in the memory alternatelyin a mode of memory address gradation; reading data from the memory in turn; and if the data read from a first memory address is not equal to the measurement vector value written in the memory address, then outputting indication information about a memory error. The embodiment of the invention is mainly used in the test process of the memory, and can also be used in the processes of detecting theintegrity of all kinds of parallel bus signals.

Description

technical field [0001] The invention relates to the field of memory, in particular to a memory testing method and device. Background technique [0002] As processor technology continues to advance, the design and development of mass storage devices has grown exponentially over the past few years; the key component of these mass storage device redesigns is not faster processors, but the replacement of HDD. The reliability of these devices depends on proper design and testing of the memory. The main goal of memory testing is to verify that each memory bit on a memory device can reliably store data. The key tests required to validate memory devices include verifying physical connections, examining every bit of memory and characterizing the device. [0003] Common memory test methods include scanning graphics method, stride graphics method, checkerboard graphics method, five-step checkerboard method, etc.; there are many schemes, and the test complexity is different, but the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/04
Inventor 谭斯乐
Owner HUAWEI TECH CO LTD