System and method for performing locked operations

Abstract

A mechanism for performing locked operations in a processing unit. A dispatch unit may dispatch a plurality of instructions including a locked instruction and a plurality of non-locked instructions. One or more of the non-locked instructions may be dispatched before and after the locked instruction. An execution unit may execute the plurality of instructions including the non-locked and locked instruction. A retirement unit may retire the locked instruction after execution of the locked instruction. During retirement, the processing unit may begin enforcing a previously obtained exclusive ownership of a cache line accessed by the locked instruction. Furthermore, the processing unit may stall the retirement of the one or more non-locked instructions dispatched after the locked instruction until after the writeback operation for the locked instruction is completed. At some point in time after retirement of the locked instruction, the writeback unit may perform a writeback operation associated with the locked instruction.

Description

technical field [0001] The present invention relates to microprocessor architectures, and more particularly to a mechanism for performing locked operations (hereinafter also referred to as "locked operations"). Background technique [0002] The x86 instruction set provides several instructions for implementing locking operations. A locked instruction (hereinafter also referred to as a "locked instruction") is automatic, that is, the locked instruction ensures that no other processor ( or other agents that can access system memory) will change the contents of that memory location. Locking operations are commonly used by software to synchronize multiple entities reading and updating shared data structures in a multiprocessor system. [0003] In various processor architectures, lock instructions are usually stalled in the dispatch stage of the processor pipeline until all older instructions have been retired and the associated memory writes back ( writeback) operation has be...

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Problems solved by technology

[0004] In such systems, since the lock instruction and all younger instructions are delayed in the scheduling phase until the older operation completes, the processor is delayed in an event equal to the delay from scheduling until the end (i.e., the writeback of the older instruction operation) usually does not function effectively during the length of the pipeline before the occurrence of

Delaying the scheduling and execution of these instructions will greatly affect the performance of the processor

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