Erasing voltage rise control circuit of flash memory

Abstract

The invention discloses an erasing voltage rise control circuit of a flash memory, at least comprising a charge pump, a sampling circuit, a controllable-duty-cycle pulse generating circuit, a reference voltage generating circuit, a first capacitor and a comparison circuit, wherein the charge pump is used for generating an erasing voltage; the sampling circuit is used for sampling the erasing voltage; the controllable-duty-cycle pulse generating circuit is used for generating a pulse with a controllable duty-cycle; the reference voltage generating circuit is connected with a power supply voltage and the controllable-duty-cycle pulse generating circuit so as to generate a reference voltage under the control of the controllable-duty-cycle pulse generating circuit; the first capacitor is connected between the reference voltage generating circuit and the ground; and the comparison circuit is used for comparing a sampling voltage with the reference voltage so as to generate a feedback signal to the charge pump. In the invention, because reference current and charging current are not generated by virtue of high-voltage output of the charge pump, extra current loads can not be generated to the output of the charge pump, no voltage loss is generated, and the rise time of the erasing voltage is more accurate.

Description

Flash memory erase voltage rise control circuit technical field The present invention relates to an erasing voltage rise control circuit, in particular to a flash memory erasing voltage rise control circuit. Background technique In a flash memory, especially a low-voltage flash memory device, it is often necessary to generate an erasing voltage through a charge pump (ChargePump). Since the erasing voltage generated by the charge pump without any restrictions often deviates from the required value, in the prior art flash memory, a control circuit is usually set to control the erasing voltage output by the charge pump. Fig. 1 is a circuit structure diagram of an erasing voltage control circuit of a flash memory in the prior art, as shown in Fig. 1, the control circuit includes a charge pump 11, a pulse generation circuit 12 with a controllable duty ratio, a PMOS transistor P1, The mirror constant current source 13, capacitor C and NMOS transistor N2 formed by P2 and NMOS t...

AI Technical Summary

Problems solved by technology

In order to overcome the problem that the erasing voltage rise time of the flash memory erasing voltage rise control circuit in the prior art is inaccurate, resulting in the inability to perform accurate and quick subsequent circuit processing, the main purpose of the present invention is to provide a flash memory erasing voltage The rise control circuit, through the negative feedback of the system and the reference current and charging current generated by the supply voltage, avoids the extra current load on the high voltage output of the charge pump, so that the rise time of the erasing voltage is more accurate

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