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PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder

A technology of LDPC code and decoding algorithm, applied in the field of integrated circuit design, can solve the problems of the maximum clock frequency and decoding rate of the decoder, and the deterioration of bit error performance.

Inactive Publication Date: 2012-02-08
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Note that the larger the value of K, the more frequently this happens, the worse the bit error performance is
Therefore, it is difficult to divide the critical path using pipeline registers, and the maximum clock frequency and decoding rate of the decoder are limited

Method used

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  • PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder
  • PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder
  • PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder

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Embodiment Construction

[0021] The implementation method of the circuit will be further explained in conjunction with the diagram below:

[0022] Use below figure 2 The LDPC code corresponding to the parity check matrix is ​​taken as an example to describe the decoder design of the present invention. image 3 Shown is the hardware design structure of the decoder based on PLDA proposed by the present invention. The check node and the variable node are combined into a single computing node, and there are 12 computing nodes (32) in total. Each computing node is inserted into 4 sets of pipeline registers to divide this critical path and increase the maximum clock frequency of the system several times. The value of Λ in equation [1] is stored in the register chain, and the decoder uses two such register chains (31), (32) to form a ping-pong structure. Each chain contains 2304 register storage units to store the value of Λ, if each value of Λ is represented by M ratio specific points, then each registe...

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Abstract

The invention belongs to the technical field of designs of integrated circuits and particularly relates to a PLDA (parallel layered decoding algorithm)-based LDPC (low density parity check) decoder. The design of the decoder is based on the PLDA, input data to be decoded is stored in register chains; the decoder has a ping pong structure by using the two register chains, namely when one register chain receives new data to be decoded and simultaneously outputs the decoded data, the other register chain with the data to be decoded is divided into M subchains and carries out decoding operation, wherein the M is equal to the number of arrays of submatrixes in an LDPC check matrix; and each subchain corresponds to an array of submatrixes in the check matrix and stores the data to be decoded corresponding to the array of submatrixes. The LDPC decoder prevents excess storage units from being used in chip designs by using the register chains so as to further reduce the chip area of the PLDA-based decoder and maintain a relatively high decoding rate.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to an LDPC code decoder based on a parallel layered decoding algorithm. Background technique [0002] In recent years, LDPC codes have attracted attention due to their excellent error correction performance. The LDPC layered decoding algorithm (Layered Decoding Algorithm, LDA) based on the minimum sum product algorithm can be described by the following equation: [0003] [1] [0004] [2] [0005] [3] [0006] In the above formula, α represents the correction factor, and the value is generally around 0.8; q represents the information passed from the variable node to the check node; Λ represents the information stored in the variable node; r represents the information passed from the check node to the variable node. LDA divides the check matrix of LDPC code into several layers vertically. Each dec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 叶凡姚远任俊彦许俊李宁李巍
Owner FUDAN UNIV