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Method for carrying out fault injection on two-path signal lines simultaneously

A technology of fault injection and signal lines, which is applied in the direction of instruments, computer control, simulators, etc., and can solve the problem of a small number of signal lines

Inactive Publication Date: 2013-11-13
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing technical equipment, only one fault signal can be injected at a time or the number of signal lines for fault injection is small, which is difficult to meet the needs of more and more complex electrical equipment.

Method used

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  • Method for carrying out fault injection on two-path signal lines simultaneously
  • Method for carrying out fault injection on two-path signal lines simultaneously

Examples

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Embodiment Construction

[0022] The present invention is a method capable of performing fault injection on two signal lines at the same time, such as figure 2 As shown, the specific steps of the method are as follows:

[0023] Step 1: Select 4 G6AU series relays produced by Omron and their driving circuits, press the relays RELAY1~RELAY4 figure 1 Connect as shown in . That is, pin 6 and pin 11 of RELAY1 are connected to each other through wires, while pin 8 and pin 9 are respectively connected to pin 4 and pin 13 of RELAY2; RELAY3 and RELAY4 are connected in the same way.

[0024] Step 2: Connect a resistor R1 in series between the 16 pin of the relay RELAY1 and the collector C of the triode D1, and the output emitter E of the triode is grounded, and the function of the resistor R1 is to prevent the current in the circuit from being too large when the triode is turned on And exceed the tolerance of components;

[0025] Step 3: A resistor R2 is connected in series between the base B of the transist...

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PUM

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Abstract

The invention relates to a method for carrying out fault injection on two-path signal lines simultaneously. The method comprises eight main steps: (1) four relays and a driving circuit are selected for connection according to a preset mode; (2) a resistor R1 is connected in series between a pin 16 of a RELAY 1 and a C electrode of a triode, and an E electrode of the triode is grounded; (3) a resistor R2 is connected in series between a B electrode of the triode and a C1 end, and the C1 end is connected at an I / O output end of a fault injection control board; (4) a C2 end is connected according to the same mode of the C1 END; (5) a VDD end and the C1-C4 ends are defaulted as high levels, at the moment, a pin 4 and a pin 6 of the relay are connected, and a pin 13 and pin 11 of the relay are connected; I1 and I2 are connected to the input end of a fault simulation board by an internal bus; O1 and O2 are connected to the output end of the fault simulation board by another internal bus; (6) when no fault is injected, external signals are injected from an IN1 / IN2 end, and are output from an OUT1 / OUT2 end; (7) when fault injection is carried out on a first-path signal line IN1 / OUT1, the relay 1 acts; and (8) if the fault injection is carried out on a second-path signal line IN1 / OUT1 simultaneously, both the relay 3 and the relay 4 act.

Description

(1) Technical field [0001] The invention relates to a method capable of performing fault injection on two signal lines at the same time, and belongs to the technical field of testing engineering of multi-channel signal fault injection. (2) Technical background [0002] At the current stage of product development and testing, there is still a lack of effective verification methods for the product's fault handling capabilities. In many cases, it is only when a failure occurs on site that the inadequacy of the system's failure handling mechanism is known. This kind of situation will reduce the service life of the equipment and in serious cases will threaten the life safety of the staff, etc. Therefore, it is urgent to implement perfect fault injection methods for the system in the laboratory to detect problems in the system fault handling mechanism early , to verify the self-protection and repair capabilities of the equipment under abnormal conditions such as component failure...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05B19/042
Inventor 石君友纪超
Owner BEIHANG UNIV
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