Division method and division device
A division and signal technology, used in instruments, electrical digital data processing, digital data processing components, etc., can solve the problem that current-mode logic cannot effectively increase the anti-noise capability, and achieve the effect of reducing noise jitter
Active Publication Date: 2015-11-18
SILICON MOTION INC (CN)
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Problems solved by technology
[0003] The technical problem to be solved by the present invention is that, aiming at the defect that the current-mode logic circuit architecture used in the prior art still cannot effectively increase the anti-noise capability, it provides a method that can operate in a high-speed / high-frequency environment and can effectively reduce signal noise. The noise jitter division device and related division method to solve the above problems
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[0039] Please refer to figure 1 , figure 1 is a schematic block diagram of the dividing device 100 according to the first embodiment of the present invention. The division device 100 includes a frequency division circuit 105 and a noise removal circuit 110. The frequency division circuit 105 is used to receive a first frequency signal and generate a frequency-divided signal S2 corresponding to the first frequency signal. The denoising circuit 110 is coupled to the frequency dividing circuit 105 and used to receive the second frequency signal and the frequency-divided signal S2, and refer to the second frequency signal and the frequency-divided signal S2 to reduce the noise of the frequency-divided signal S2 to generate a frequency-divided signal S2. Noise-divided signal DIV2. In this embodiment, the signal sources of the first frequency signal and the second frequency signal are the same frequency signal source CK. In other words, the second frequency signal is the first fre...
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The invention provides a division device. The division device comprises a frequency division circuit and a denoising circuit, wherein the frequency division circuit is used for receiving a first frequency signal and generating a signal after frequency division corresponding to the first frequency signal, the denoising circuit is coupled to the frequency division circuit and is used for receiving a second frequency signal and a signal after frequency division corresponding to the second frequency signal, and reducing noise of the signal after frequency division by referring to the second frequency signal and the signal after frequency division to generate a denoised signal after frequency division. The first frequency signal and the second frequency signal can be same or different. A current-type logic circuit structure realized according to the invention can be operated under a high-speed / high-frequency environment and can be used for effectively reducing the noise jittering in the signals.
Description
technical field [0001] The present invention relates to a division mechanism, and more specifically, relates to a division device and a division method that can operate in a high-speed / high-frequency environment and can effectively reduce noise and jitter. Background technique [0002] Generally speaking, the circuit architecture used by traditional dividers is the circuit architecture of CMOS Standard Cell. However, in order to improve the tolerance of the circuit itself to noise and jitter, some dividers use current-mode logic. (CurrentModeLogic, CML) circuit architecture to replace the original circuit architecture of complementary metal oxide semiconductor standard components. Such an implementation method will relatively increase the area of the chip and increase additional power consumption, but in some cases (such as high-speed / high-frequency operating environments), the current-mode logic circuit architecture currently used is still unable to Effectively increase ...
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IPC IPC(8): G06F7/535
Inventor 洪硕钧
Owner SILICON MOTION INC (CN)