Layouts of poly cut openings overlapping active regions

Abstract

A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

Description

technical field [0001] The invention relates to the field of semiconductors, and more specifically, to a layout of POLY cutouts. Background technique [0002] As the gate electrode pitch is reduced, its pitch is often referred to as POLY pitch, increasingly stricter design rules are adopted. For example, a fixed poly pitch is required for a POLY pitch of 90nm or less, in which gate electrodes and dummy gate electrodes in a wafer are formed as parallel lines with a uniform pitch. [0003] Under limited design rules, there is limited space for forming well pick-up regions since they are usually formed between parallel POLY lines. A well pickup region is necessary for this circuit. However, the well pickup region also occupies chip area, and it is difficult to reduce the chip area loss caused by the well pickup region. Contents of the invention [0004] In order to solve the defects existing in the prior art, according to one aspect of the present invention, a method is pr...

AI Technical Summary

Problems solved by technology

However, the well pickup region also occupies the chip area, and it is difficult to reduce the chip area loss caused by the well pickup region

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