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Multi-core processor sytem, control program, and control method

A technology of multi-core processors and control methods, which is applied in the directions of multi-program device, program control design, program startup/switching, etc., can solve the problems of interrupt response delay and achieve the effect of high-speed response time

Inactive Publication Date: 2012-12-12
FUJITSU LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention improves how fast processing cores handle more important tasks by allowing them faster when they are interrupted or waiting for data from other parts of their memory hierarchy. This helps improve overall performance efficiency on multiple levels within these systems.

Problems solved by technology

This patents describes different ways how hardware or software interrupt signals affect computer performance. One way they address involves assigning them priority based upon their importance level. Another approach focuses on improving efficiency at executing certain functions within one process while minimizing delays associated with other processes.

Method used

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  • Multi-core processor sytem, control program, and control method
  • Multi-core processor sytem, control program, and control method
  • Multi-core processor sytem, control program, and control method

Examples

Experimental program
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Embodiment 1）

[0060] Figure 7 It is an explanatory drawing showing Example 1. First, (1) when a hardware interrupt request is issued to the main CPU 101 via the I / O device 103 , the main OS 121 (2) immediately withdraws the task A being executed by the main CPU 101 .

[0061] Then, the main OS 121 ( 3 ) executes the hardware interrupt processing program of the hardware interrupt request. Then, the main OS 121 uses the process table 151 to specify the CPU assigned the task of receiving the interrupt by the software interrupt handler called by the hardware interrupt handler. Here, the task that received the interrupt is defined as task B, and the slave CPU 102 is specified as the CPU to which task B is assigned. Then, master OS 121 ( 4 ) notifies slave CPU 102 of a software interrupt request through interprocessor interrupt communication.

[0062] The hypervisor 112 monitors the interprocessor communication and detects the software interrupt request. When the hypervisor 112 detects a sof...

Embodiment 2）

[0074] In the second embodiment, it is explained that based on whether the task in execution is allowed to be interrupted, it is judged that a software interrupt handler with a high priority is executed immediately, or that the software interrupt handler is executed when the task in execution ends or a task is switched. example.

[0075] Here, in the second embodiment, when the task being executed does not allow interruption, the flag indicating whether the task being executed has ended or whether a task switching has occurred is set to ProcessID. If the ProcessID is 0, it means that the task is being executed; if the ProcessID is 1, it means that the task being executed has ended or a task switch has occurred.

[0076] Figure 10 It is an explanatory diagram showing an example of the use case table of the second embodiment. In the use case table 1000, there is information indicating for each function whether to forcibly execute processing at the time of interruption, inform...

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Abstract

A hypervisor (112) monitors inter-processor communication, and upon detection of a software interrupt request, the software interrupt handler for the detected software interrupt request determines whether or not the processing is of high priority. Upon the software interrupt handler determining the processing to be of high priority, the hypervisor (112) (5) generates a pseudo hardware interrupt request for a slave CPU (102). A slave OS (122) (6) saves a task B in execution to the head of a ready queue, and (7) executes the software interrupt handler prior to task B.

Description

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Claims

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Application Information

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Owner FUJITSU LTD
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