Packaging substrate and manufacturing method thereof

A technology for packaging substrates and manufacturing methods, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices, etc., to ensure the effect of signal transmission and reliable electrical connection structure.

Inactive Publication Date: 2013-02-13
ASE SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of this, the present invention provides a packaging substrate and its manufacturing method to solve the problem of the structural reliability of the circuit substrate existing in the prior art

Method used

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  • Packaging substrate and manufacturing method thereof
  • Packaging substrate and manufacturing method thereof
  • Packaging substrate and manufacturing method thereof

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Embodiment Construction

[0015] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. Furthermore, the directional terms mentioned in the present invention, such as "upper", "lower", "top", "bottom", "front", "back", "left", "right", "inside", " Outer, Side, Surround, Center, Horizontal, Horizontal, Vertical, Longitudinal, Axial, Radial, Topmost, or Bottommost etc. are merely for reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

[0016] Please refer to figure 1 As shown, the package substrate 1 of an embodiment of the present invention mainly includes: a first dielectric layer 10a, at least one first conductive pillar 11a, a second circuit layer 12, a seed layer 13', a first circuit layer 14 , a second dielectric layer 10b and at least one ...

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Abstract

The invention discloses a packaging substrate, and a manufacturing method of the packaging substrate, wherein the packaging substrate comprises a first dielectric layer; at least one first conductive pole which is formed in the first dielectric layer; a seed layer which is covered on an upper surface of the first dielectric layer and is provided with at least one opening corresponding to the first conductive pole; and a first circuit layer which is formed on the seed layer, electrically connected with the first conductive pole through an opening and is arranged corresponding to the seed layer.

Description

technical field [0001] The present invention relates to a packaging substrate and a manufacturing method thereof, in particular to a packaging substrate capable of increasing the bonding reliability of interlayer via holes and a manufacturing method thereof. Background technique [0002] Nowadays, in order to meet various high-density and miniaturized packaging requirements in the semiconductor packaging industry for more active and passive components and circuit loading, semiconductor packaging has gradually developed from double-layer circuits to multi-layer circuit boards (multi- layer circuit board), using interlayer connection technology (Interlayer connection) in a limited space to expand the available circuit layout area on the semiconductor package substrate (substrate), in order to meet the needs of integrated circuits with high circuit density, and reduce the thickness of the package substrate , to accommodate a larger number of circuits and electronic components u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768
Inventor 王德峻黄建华罗光淋方仁广
Owner ASE SHANGHAI
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