Stress Enhanced Semiconductor Devices

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source / drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source / drain stressor device that is disposed in the substrate. The source / drain stressor device is disposed between the gate and the trench liner.

Description

technical field [0001] The present invention relates to semiconductor devices and, in particular, to stress-enhanced semiconductor devices. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to realize these advances. During the development of integrated circuits, functional density (ie, the number of interconnected devices per chip area) has increased substantially, while geometry size (ie, the smallest element (or line) that can be made using a fabrication process) has decreased. This scaling down process generally benefits by increasing production efficiency and reducing...

AI Technical Summary

Problems solved by technology

Thus, while existing strained transistor devices are generally adequate for their intended purposes, they are not entirely satisfactory in all respects.

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