Semiconductor memory device having three-dimensionally arranged resistive memory cells

Abstract

Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2011-0124204 filed on Nov. 25, 2011, the entire contents of which are incorporated herein by reference. technical field [0003] Example embodiments of inventive concepts relate to semiconductor memory devices, and more particularly, to semiconductor memory devices having three-dimensionally arranged resistive memory cells. Background technique [0004] Three-dimensional integrated circuit (3D-IC) memory technology can be used to increase memory capacity. The 3D-IC memory technology generally refers to a technology related to three-dimensionally arranging memory cells. In addition to 3D-IC memory technology, memory capacity can also be increased by (1) pattern miniaturization technology and (2) multi-level cell (MLC) technology. However, the use of pattern miniaturization techniques can be limited due to high cost, and the increase in capacity ach...

AI Technical Summary

Problems solved by technology

However, the use of pattern miniaturization technology will be limited due to high cost, and the capacity increase achieved by MLC technology will be limited by the number of bits to be increased in each cell

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