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Signal block sequence processing method and signal block sequence processing device

一种处理方法、信号的技术，应用在多路复用通信、通过路径配置进行数据交换、传输系统等方向，能够解决耐性低、纠错符号冗余比特长度不充分、突发错误长度短等问题，达到提高错误耐性的效果

Active Publication Date: 2013-09-11
NIPPON TELEGRAPH & TELEPHONE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0021] In addition, in Non-Patent Document 7, since the redundant bit deleted from one block is only one bit, the redundant bit length of the error correction symbol for the information bit length is not sufficient, and the burst error length that can be corrected is shorter
Furthermore, the error correction symbols used are specialized for correction of burst errors, so they are less resistant to random errors

Method used

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  • Signal block sequence processing method and signal block sequence processing device
  • Signal block sequence processing method and signal block sequence processing device
  • Signal block sequence processing method and signal block sequence processing device

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no. 1 approach

[0129] As described above, according to the present invention, the signal block composed of the signal block payload and the signal block header is processed to output a super block. In a series of processing, the signal block header is deleted and the bit rate used to transmit the super block is suppressed. In addition, according to the present invention, a super block is processed, and a signal block that becomes the basis of the super block is output.

[0130] Hereinafter, the first embodiment of the present invention will be described with reference to the drawings.

[0131] figure 1 It is a diagram showing the outline of the processing procedure of the signal block. in figure 1 In this case, Bd' is used to represent the signal block payload that stores data (referred to as data block payload in this specification), and Bc' is used to represent the signal block payload that stores control codes (referred to as control block effective in this specification). Load). In additio...

no. 2 approach

[0186] As described above, according to the present invention, a string of signal blocks composed of a signal block payload and a signal block header is input, the input signal block string is processed, and a super block is output. In a series of processing, the signal block header and part or all of the signal block payload composed only of characters for clock adjustment are deleted, and the bit rate for transmitting the super block is suppressed. In addition, according to the present invention, the input super block is processed, and the signal block that becomes the basis of the super block is output (restored).

[0187] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

[0188] Figure 15 It is a diagram showing the outline of the processing procedure of the signal block. in Figure 15 Here, B represents the string of input signal blocks. Let Bd' represent the payload of the signal block storing data, and let Bc' rep...

no. 3 approach

[0255] As described above, according to the present invention, on the receiving side, the super block generated on the transmitting side is received, and the determination of whether or not all the position identification information is overlapped and used by the control block payload in the super block payload The predetermined condition of all block type values ​​stored in the control block payload in the super block payload is determined, and error detection is performed. In this way, erroneous transmissions are eliminated. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

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Abstract

A signal block sequence processing method, which makes it possible to make use of a standard existing system even in the case where there is a difference in interface speed between a LAN and a WAN, deletes a signal block header from each of sequences of signal block (B) comprised of signal block headers (Bch, Bdh) to identify whether a signal block payload is a control block payload (Bc') that stores a control code or a data block payload (Bd') that stores data, collectively makes one group (G), gives the control block payload in the group position identification information to identify a position of the control block payload in the group, rearranges a signal block payload in compliance with the signal block payload rearrangement rule known on a receiving side, stores the rearranged signal block payload at a super block payload (Sc), and outputs a super block (S); to which a super block header (Shc) to identify the inclusion of the control block payload is added.

Description

Technical field [0001] The present invention relates to a signal block string processing method and a signal block string processing device for processing a string of signal blocks composed of a signal block payload and a signal block header. More specifically, it relates to a signal transmission device and a signal transmission system. A signal block string processing method and a signal block string processing device for processing a block string to output a super block and / or meta super block. Background technique [0002] The Ethernet (registered trademark) technology developed as a LAN (Local Area Network) technology has an increasing sense of existence in a WAN (Wide Area Network), and most of the Ethernet services are transmitted via the WAN. [0003] When transmitting an Ethernet signal via an electrical / optical cable, in order to facilitate transmission, the bit string provided from the upper layer is not transmitted as it is, but is encoded and transmitted. For example, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/46H04J3/00
CPCH04L12/4625H04J3/1658H04J2203/0085H04L1/0083H04L12/4633H04L25/4917H04L69/22
Inventor 小林正启手岛光启山本猛仁石田修木坂由明
Owner NIPPON TELEGRAPH & TELEPHONE CORP
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