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Instruction Fetch Method for Pipeline Structure Processor Using Variable Length Instruction Set

A variable-length instruction and pipeline technology, applied in the field of instruction fetching

Active Publication Date: 2015-11-25
TONGJI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a method for fetching instructions for a pipeline structure processor using a variable-length instruction set in order to overcome the above-mentioned defects in the prior art. No increase in memory depth and no decrease in throughput of the processor pipeline

Method used

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  • Instruction Fetch Method for Pipeline Structure Processor Using Variable Length Instruction Set
  • Instruction Fetch Method for Pipeline Structure Processor Using Variable Length Instruction Set
  • Instruction Fetch Method for Pipeline Structure Processor Using Variable Length Instruction Set

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Embodiment

[0027] Such as Figure 1~3 As shown, an instruction fetching method for a pipelined structure processor adopting a variable-length instruction set includes an instruction fetching stage, a decoding stage, and an instruction data circular buffer (InstructionBuffer, IB) of the pipeline. Among them, the instruction fetch stage includes: instruction memory (InstructionMemory, IM), instruction fetch address register (memPC), instruction fetch decision unit (FetchDecision, FD); pipeline decoding stage includes: instruction decoding module (InstructionDecoder, ID), decoding The code address register (PC); the instruction data circular buffer is part of the pipeline register between the fetch stage and the decode stage.

[0028] Wherein, the width of the instruction memory is the maximum length of a single instruction, and instructions of different lengths are continuously stored in the instruction memory. Taking the instruction lengths of 4 bytes and 8 bytes as examples, the word le...

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Abstract

The invention relates to an instruction fetching method for a pipeline organization processor using lengthened instruction sets. The instruction fetching method for the pipeline organization processor using the lengthened instruction sets comprises the steps that (1) instructions with different widths are adopted and are continuously stored on an instruction memory, and an instruction fetching pointer and a decoding pointer are arranged to be used for storing a next address needing instruction fetching and a next address needing decoding; (2) an instruction data circulating buffer area with a certain width is arranged in an instruction fetching component, data fetched from the instruction memory need to cover a specific portion of the instruction data circulating buffer area, and the data are fetched from the specific portion of the instruction data circulating buffer area to carry out decoding in an instruction fetching stage; (3) whether instruction fetching needs to be carried out on the next cycle or not is determined according to the decoding result and the two pointers. Compared with the prior art, the instruction fetching method for the pipeline organization processor using the lengthened instruction sets can solve the problem of instruction fetching of the lengthened instruction sets, and meanwhile ensures the facts that the depth of the instruction memory is not increased, and the handling capacity of a pipeline of the processor is not reduced.

Description

technical field [0001] The invention relates to an instruction fetching method, in particular to an instruction fetching method for a pipeline structure processor adopting a variable-length instruction set. Background technique [0002] The so-called instruction set is a set of instructions used in the CPU to calculate and control the computer system, and each new type of CPU specifies a series of instruction systems that cooperate with other hardware circuits when it is designed. Whether the instruction set is advanced or not is also related to the performance of the CPU, and it is also an important symbol of the performance of the CPU. [0003] In the modern age of rapid technological development, as the design of ASIP becomes more and more complex, the design of instruction sets is no longer limited to the traditional RISC mode. Technologies such as VLIW and SIMD have also been widely used in instruction set design. VLIW: (VeryLongInstructionWord, very long instruction w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
Inventor 吴俊骆原张志峰苏立峰陈伟沈嘉琦
Owner TONGJI UNIV