Instruction Fetch Method for Pipeline Structure Processor Using Variable Length Instruction Set
A variable-length instruction and pipeline technology, applied in the field of instruction fetching
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[0027] Such as Figure 1~3 As shown, an instruction fetching method for a pipelined structure processor adopting a variable-length instruction set includes an instruction fetching stage, a decoding stage, and an instruction data circular buffer (InstructionBuffer, IB) of the pipeline. Among them, the instruction fetch stage includes: instruction memory (InstructionMemory, IM), instruction fetch address register (memPC), instruction fetch decision unit (FetchDecision, FD); pipeline decoding stage includes: instruction decoding module (InstructionDecoder, ID), decoding The code address register (PC); the instruction data circular buffer is part of the pipeline register between the fetch stage and the decode stage.
[0028] Wherein, the width of the instruction memory is the maximum length of a single instruction, and instructions of different lengths are continuously stored in the instruction memory. Taking the instruction lengths of 4 bytes and 8 bytes as examples, the word le...
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