Wafer yield analysis method and system thereof

Abstract

The invention provides a wafer yield analysis method which comprises the following steps of dividing each chip into a plurality of function areas according to functions, carrying out surface detection on each chip respectively, obtaining the defect information of one or more function areas according to a function area to which a detected defect belongs in the chip, carrying out yield testing on each chip respectively to obtain chip yield information, carrying out comparison and analysis on the defect information of one or more function areas and the chip yield information to obtain qualified chips without defacement, qualified chips with defacement, unqualified chips without defacement and unqualified chips without defacement which are divided according to one or more function areas and calculating the fatal defect rate of one or more function areas of the chip, obtaining the overall fatal defect rate of the chip through the fatal defect rate of one or more function areas, and predicating the wafer yield according to the overall fatal defect rate of the chip. At the same time, the invention provides a wafer yield analysis system.

Description

【Technical field】 [0001] The invention relates to the technical field of semiconductors, in particular to a wafer yield analysis method and system. 【Background technique】 [0002] In the daily semiconductor manufacturing process, a crystal column (lot) refers to a silicon columnar body generated in a certain way, and these crystal columns are cut into thin slices to be called a wafer (wafer), and a wafer is a substrate for integrated circuit manufacturing. Generally distinguished by diameter, 8 inches, 10 inches, 12 inches, etc., or by millimeters. The larger the diameter, the higher the utilization rate of the material, because the periphery of the wafer cannot be utilized due to the arc shape. Divide different areas on the wafer according to needs, and each area is used to produce chips (die) with specific functions. A wafer can be of the same type of chips or different types of chips. The latter can be called a multi-project wafer, which allows multiple units with a sma...

AI Technical Summary

Problems solved by technology

In order to predict the wafer yield rate, the traditional fatal defect rate estimation is carried out through the fatal defect rate of the chip. The traditional fatal defect rate of the chip is only limited to the level of the chip. As long as the chip has a defect, the chip will be defined as a defective chip. Defects in non-critical areas such as the edge of a single chip will also be considered. Therefore, simply using the fatal defect rate estimation at the chip level to predict the yield of the chip will lead to inaccurate prediction results and unsatisfactory results.

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