Multi-phase delay phase-locked loop and control method thereof

Abstract

The invention discloses a multi-phase delay phase-locked loop and a control method thereof. The multi-phase delay phase-locked loop comprises a delay part, a searching part and a control part, wherein the delay part is provided with a plurality of delay units used for outputting a multi-phase clock, the searching part is connected with the delay units and is used for searching for a target delay unit, and the control part is connected with the searching part and the delay units and is used for receiving the target delay unit sent by the searching part, prolonging delay time of the target delay unit, controlling the delay part to work in a second mode, obtaining the maximum delay time of the delay part, and controlling the delay part to work in a first mode if the maximum delay time does not reach a clock period of a system clock signal, and otherwise, controlling the delay part to output the multi-phase clock. By means of the multi-phase delay phase-locked loop and the control method, the problem that in the prior art, phase precision of a multi-phase delay phase-locked loop output clock is low, and therefore the effect of improving the phase precision of the multi-phase output clock is achieved.

Description

technical field [0001] The invention relates to the field of clock circuits, in particular to a multi-phase delay-locked loop and a control method thereof. Background technique [0002] Delay-locked loop circuits are widely used in high-speed circuit systems to generate multi-phase clocks. The multi-phase delay-locked loop can generate N output clocks CK1, CK2, CK3...CKN of the same frequency according to one input clock, and the N output clocks have an equal interval phase relationship (N is an integer, generally 4, 8, 16, etc.). Therefore, the function of the multiphase delay-locked loop can be defined as: generate N output clocks according to the input clock, and the phase difference between the N output clocks is [0003] A four-phase clock generation circuit is disclosed in the related art, and the four-phase clock generation circuit adopts figure 1 The structure shown is mainly composed of four digitally controlled delay chains connected in series, the control cir...

AI Technical Summary

Problems solved by technology

[0006] The main purpose of the present invention is to provide a multi-phase delay-locked loop and its control method to solve the problem of low phase accuracy of the output clock of the multi-phase delay-locked loop in the prior art

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