Static random memory unit

Abstract

The invention discloses a static random memory unit, comprising a first inverter, a second inverter, a first feedback resistor, a second feedback resistor, a first feedback transistor and a second feedback transistor. The first feedback resistor and the first feedback transistor are in parallel connection and coupled to an output terminal of the first inverter and an input terminal of the second inverter; and the second feedback resistor and the second feedback transistor are in parallel connection and coupled to an input terminal of the first inverter and an output terminal of the second inverter. The invention can effectively improve single event upset resistance of the static random memory, and further ensure that the static random memory unit has high reading and writing speed in the states of reading and writing.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random storage unit resistant to single event reversal effect. Background technique [0002] Static random access memory unit (SRAM unit) is the most commonly used semiconductor memory, which has the advantages of high speed and low power consumption. At present, the most common SRAM unit structure in the industry is six-tube SRAM, such as figure 1 As shown, it consists of 6 transistors. The PMOS transistor P11 and the NMOS transistor N11 constitute the first inverter INV1, and the PMOS transistor P22 and the NMOS transistor N22 constitute the second inverter INV2. Two inverters are cross-locked, that is, the output terminal S1 of the first inverter INV1 and the input terminal of the second inverter INV2 (that is, the gates of the PMOS transistor P22 and the NMOS transistor N22 ), and the output terminal S2 of INV2 is connected with the input terminal Q of INV...

AI Technical Summary

Problems solved by technology

[0005] Although the introduction of resistance or capacitance in the SRAM unit can effectively achieve the purpose of suppressing single event flipping, it is not difficult to find that adding resistance or capacitance between the two inverters will inevitably greatly reduce the read and write speed of the SRAM unit

Usually, in order to effectively suppress single event flipping, the feedback resistance introduced in the SRAM unit needs to reach the order of mega-ohms. This high-resistance element makes it difficult to guarantee the read and write stability of the SRAM.

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