Packaging method for wafer-level chip
A wafer-level chip and packaging method technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as invisible dicing lanes
Active Publication Date: 2014-02-12
ALPHA & OMEGA SEMICON INT LP
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Problems solved by technology
Although this method is extremely effective in preventing wafer fragmentation, it causes the scribe line to be covered by the plastic layer and cannot be seen at the same time. Because the plastic material usually used is not a transparent substance, how to align the cutting knife on the The frontal scribe lane becomes a tricky problem
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Embodiment Construction
[0041] see Figure 1A In the top view shown, the wafer 100 usually includes a large number of chips 101 that are cast and connected together. The schematically shown multiple criss-crossing dicing lines (Scribe lines) are located on the front of the wafer 100, and they define the gaps between adjacent chips. At the same time, the chip 101 can be cut and separated from the wafer 100 along the cutting line. Usually, the front side of any chip 101 is pre-prepared with several metal pads (not shown in the figure) as electrodes for connecting the chip to power supply, grounding, or terminals for signal transmission with external circuits, etc., because these technical features have been It is well known to those skilled in the art, so it will not be repeated here.
[0042] see Figure 1B As shown, at least one metal bump 110 is correspondingly soldered on any metal pad on the front side of any chip 101. There are many kinds of metal bumps 110, such as copper, gold, silver, Alumin...
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The invention generally relates to a manufacturing method of a semiconductor device, and precisely aims to provide a packaging method, and according to the packaging method, a thinner chip is obtained in the packaging step of the wafer-level chip to improve the mechanical strength of a wafer. The packaging method includes the steps that a metal bump is firstly welded to a metal bonding pad of the chip, a first round plastic package layer is then formed and covers the front face of the wafer, the first plastic package layer is grinded to be thinned, and then the first plastic package layer is cut to form a corresponding cutting groove. The back face of the wafer is grinded to form a cylindrical groove, a metal layer is deposited on the bottom surface, exposed in the cylindrical groove, of the wafer, the periphery part of the wafer is cut off, and the first plastic package layer, the wafer and the metal layer are cut along the cutting groove.
Description
technical field [0001] The present invention generally relates to a method for preparing a semiconductor device. More specifically, the present invention aims to provide a packaging method for obtaining a thinner chip and improving the mechanical strength of the wafer during the wafer-level chip packaging step. Background technique [0002] In wafer-level chip-scale packaging (WLCSP) technology, after the entire wafer is produced, the wafer can be directly packaged, and then multiple single dies are separated from the wafer, so the final obtained chip The size is almost equal to the size of the original grain. The current wafer-level packaging technology is also widely used in power semiconductor devices. We all know that in power devices, the resistance of the chip itself is often relatively large, especially vertical devices, so the device will have a large On-state resistance Rdson. An effective means to improve substrate resistance is to thin the wafer as much as possi...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L21/56H01L21/78
CPCH01L2224/32245H01L2224/73253H01L2224/94H01L2224/97H01L2924/13091H01L2224/11H01L2224/83H01L2924/00H01L21/563H01L21/78H01L24/14
Inventor 薛彦迅哈姆扎·耶尔马兹何约瑟鲁军黄平石磊段磊龚玉平
Owner ALPHA & OMEGA SEMICON INT LP