Charge matching-based offset correction method of full-symmetric four-terminal dynamic comparator

Abstract

The invention discloses a charge matching-based offset correction method of a full-symmetric four-terminal dynamic comparator. The charge matching-based offset correction method includes the following steps that: a comparator is controlled to come into an offset correction state according to clock signals, reset signals and correction signals; common-mode electric level signals are inputted into the input end of the comparator; and an adjustable capacitor connected with the output end of the comparator is controlled, so that the output positive and negative end charges of the comparator can be matched under the effect of the adjustable capacitor, wherein the adjustable capacitor can be formed through short circuiting of the source and the drain of an NMOS transistor. With the charge matching-based offset correction method of the full-symmetric four-terminal dynamic comparator of the invention adopted, influence of floating nodes on the speed and accuracy of the comparator can be eliminated, and offset caused by various factors in the dynamic comparator can be eliminated, and circuit accuracy can be improved. The invention also provides a charge matching-based offset correction system of the full-symmetric four-terminal dynamic comparator.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an offset correction method and system for a fully symmetrical four-terminal dynamic comparator based on charge matching. Background technique [0002] High-speed successive approximation analog-to-digital converters are mostly used in radio frequency front-end receivers of wireless sensor networks. In this application, high-speed, medium conversion accuracy and low power consumption analog-to-digital converters have a significant impact on system performance. [0003] The successive approximation analog-to-digital converter mainly includes four parts: sample-and-hold circuit, digital-to-analog converter, comparator and digital control logic. Among them, the comparator is the main source of power consumption in the successive approximation analog-to-digital converter, and is mainly divided into static comparators and dynamic comparators. Among them, the static compar...

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But at the same time, this structure has a larger misalignment and is more susceptible to noise interference

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