64results about How to "Low misalignment" patented technology

The invention relates to a wavelet transform and variable-step least mean square algorithm-based voice denoising method. The method is technically characterized by comprising the following steps of: reducing the dispersion degree of an input vector self-correlation matrix characteristic value of an adaptive filter by using a time-frequency local characteristic of a wavelet, and increasing step factors of the algorithm; and simultaneously, establishing a non-linear function relationship between the step factors and an error signal to ensure that the step factors are adaptively increased at the initial stage and the time change stage and are adaptively decreased at the steady state stage. The method not only can ensure a relatively high convergence speed and little maladjustment but also has certain robustness and denoising performance, so a better denoising effect can be obtained by combining the wavelet transform and the variable-step least mean square algorithm.

The invention discloses a pre-amplifying latch comparator with low detuning. The pre-amplifying latch comparator with the low detuning comprises a base pre-amplifying latch comparator, a detuning compensation geminate transistor, a detuning calibration switch and a detuning calibration control circuit. The base pre-amplifying latch comparator comprises a primary pre-amplifier and a secondary latch. The detuning compensation geminate transistor comprises a detuning adjusting transistor, the detuning adjusting transistor is connected to the output end of the pre-amplifier in parallel, and the detuning voltage of the whole comparator is regulated by changing a grid voltage of the detuning adjusting transistor. A digital bidirectional shifter is adopted by the detuning calibration control circuit to store detuning information and control the detuning calibration control circuit to carry out detuning calibration. According to the pre-amplifying latch comparator with the low detuning, the detuning calibration control circuit based on digital storage and control is added based on an existing pre-amplifying latch comparator, the detuning of the pre-amplifying latch comparator can be reduced to one nth of original detuning, and the pre-amplifying latch comparator after calibration reduces the detuning greatly.

The invention provides a circuit structure for reducing input offset voltage of a two-stage operational amplifier, which comprises a switching control circuit, a first-stage differential amplification circuit, a second-stage common-source amplification circuit and a compensation network, wherein the output end of the switching control circuit is connected with the input end of the first-stage differential amplification circuit, the output end of the first-stage differential amplification circuit is connected with the input end of the second-stage common-source amplification circuit, and the compensation network is further connected between the input end and the output end of the second-stage common-source amplification circuit. The circuit structure has the benefits that the offset of theoperational amplifier is reduced by adopting an MOS (metal oxide semiconductor) switching tube to control and exchange signals at the positive and the negative input ends and the signals at the output end of the operational amplifier; as only the MOS switching tube is increased in the circuit, the circuit structure only needs very small area and very low power consumption; and the circuit does not affect the gain of the operational amplifier, the phase margin, the power supply voltage rejection ratio, the common-mode input range and other performance indexes while reducing the input offset voltage of the operational amplifier, and can be applied in mainstream CMOS (complementary metal oxide semiconductor) circuit systems.

The invention discloses an operational amplifier offset self-calibration circuit applied to a voice coil motor driver chip. The operational amplifier offset self-calibration circuit comprises an operational amplifier (OPAMP), a counting latch, a comparator, an oscillator and a digital analog converter for calibration (DAC), wherein the output end of the OPAMP is connected with the negative pole input end of the comparator; the output end of the comparator is connected with the input end of the oscillator and one input end of the counting latch; the output end of the oscillator is connected with another input end of the counting latch; the output end of the counting latch is connected with the input end of the DAC for calibration; the output end of the DAC for calibration is connected witha signal feedback end of the OPAMP; and the input end and the output end of the OPAMP are further respectively connected with the voice coil motor driver chip. The offset of the OPAMP can be eliminated or greatly decreased, the accuracy of output current of the motor driver chip is improved, the service time of the system battery is prolonged, and the condition that the chip development and test cost is increased due to offset calibration by using a fuse wire is avoided.

The present invention discloses a dynamic comparator and a method of imbalance calibration thereof. The dynamic comparator comprises: a latch and a pre-amplifier comprising a pre-amplification circuitand a calibration auxiliary circuit; the calibration auxiliary circuit comprises a charge storage capacitor storing an imbalance voltage, a charging and discharging switch, a common mode switch, a first calibration control switch and a second calibration control switch; and the input end of the dynamic comparator is connected in series with the charge storage capacitor, and the imbalance calibration is performed through control of the charging and discharging switch, the common mode switch, the first calibration control switch and the second calibration control switch.

The invention discloses a voltage-mode switching DC-DC converter with on-chip frequency compensation, and relates to the field of analog integrated circuits. The voltage-mode switching DC-DC converter comprises an error amplifier, a PWM comparator, an oscillator, a logic control module and a power tube, wherein the power tube is provided with a VIN input end used for inputting variable DC voltage VIN. The voltage-mode switching DC-DC converter is characterized by further comprises a feedforward compensation module, wherein an output end of the feedforward compensation module is connected to a negative input end of the error amplifier, the output end of the feedforward compensation module is further grounded through a second resistor Rf2, the output end of the feedforward compensation module is further connected to an output end of the error amplifier through a third resistor Rf3, and the output end of the feedforward compensation module is connected to output voltage Vsense through a first resistor Rf1. The voltage-mode switching DC-DC converter realizes on-chip full integration of compensation components under the condition of ensuring the loop stability, so that the area of a PCB is saved, and the application cost is reduced.

The invention provides an assembly line A/D converter dynamic compensation device based on a true random number sequence. The device comprises a sub-A/D converter, a sub-D/A converter, a true random number generation circuit and a coding circuit, wherein the true random number generation circuit is used for generating the true random number sequence, and providing the true random number sequence for the sub-A/D converter to control opening and closing of a switch corresponding to a reference voltage input end of a comparator in the sub-A/D converter; the sub-A/D converter is used for providing an output digital signal for the coding circuit, and the coding circuit is used for generating a coding signal according to the digital signal and providing the coding signal for the sub-D/A converter to control the opening and closing of a switch in the sub-D/A converter. According to the device of the invention, the problem that in the sub-A/D converter, the comparator is maladjusted and capacitance in the sub-D/A converter is mismatched can be solved.

The invention discloses a low-power-consumption high-PSRR band-gap reference source. The low-power-consumption high-PSRR band-gap reference source comprises a first P-channel field-effect transistor, a second P-channel field-effect transistor, a third P-channel field-effect transistor, a fourth P-channel field-effect transistor, a fifth P-channel field-effect transistor, a sixth P-channel field-effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first double-polar-form transistor, a second double-polar-form transistor and a voltage feedback circuit. By adopting the double-layer current mirror structure and adding a biasing resistor, the influence of the channel length modulation effect between current mirrors is reduced, the accuracy of a current multiplication factor is guaranteed, and then detuning of output voltage is reduced.

The invention discloses a complementary metal oxide semiconductor (CMOS) sensor with an octagonal Hall disk structure and a manufacturing method for the CMOS sensor. The CMOS sensor comprises a p type substrate, an octagonal n well, a p+ doped region, n+ doped regions, a depletion layer, a p+ lightly doped region, an oxide layer and an aluminum layer, wherein the octagonal n well is positioned on the p type substrate; the p+ doped region is positioned outside the edge of the octagonal n well; the n+ doped regions are positioned on the inner side of the edge of the octagonal n well; the depletion layer is positioned at the boundary of the octagonal n well and the p type substrate; the p+ lightly doped region is positioned above the octagonal n well; the oxide layer is positioned on the surface of the octagonal n well; and the aluminum layer is positioned above the n+ doped regions. Due to the adoption of the octagonal Hall disk structure, eight terminals can be provided to generate eight current directions and further greatly reduce offset.

The invention discloses a circuit improving dynamic switch linearity in an analog-to-digital converter. The circuit is characterized by comprising a high voltage power generation circuit, a sampling phase clock voltage conversion circuit, and a holding phase clock voltage conversion circuit, wherein the high voltage power generation circuit mainly comprises N voltage boost units that are in parallel connection, each of the sampling phase clock voltage conversion circuit and the holding phase clock voltage conversion circuit comprises M clock voltage conversion units that are in parallel connection, the voltage boost unit mainly comprises seven inverters, two NOR gates, two NAND gates, two buffer units, six NMOS transistors and five capacitors, and the clock voltage conversion unit mainly comprises three PMOS transistors, one NMOS transistor, and a capacitor. The circuit has advantages of improving the performance of a comparator, lowering device imbalance, reducing chip area, loweringswitch power consumption, having strong output and drive capabilities, stable switch signals and so on.

The invention discloses a novel slope compensation circuit. The novel slope compensation circuit comprises a slope signal generation circuit and an upper tube current sampling circuit. The slope signal generation circuit is connected with the upper tube current sampling circuit. According to the slope signal generation circuit, a source follower structure is adopted to ensure that slope current and input voltage form a linear relationship; and an output current mirror image point potential isolation structure is adopted, so that a mirror point potential is prevented from being interfered during switch conversion. An operational amplifier circuit of the upper tube current sampling circuit adopts a BIP transistor, so that the current detection precision is improved. According to the novel slope compensation circuit of the invention, the current flowing through a sampling upper tube is superposed to a slope signal to realize slope compensation, so that the stability of a system is improved and the response time of the system is reduced; the slope generation circuit adopts the source follower structure, so that the circuit structure is simplified, and the accuracy of the slope signal is improved; and triodes with larger areas are adopted as input geminate transistors of the upper transistor current sampling circuit, so that the offset voltage is reduced, and the current compensation precision is improved.

The invention discloses a programmable time amplifier circuit with high precision and a high dynamic range. The programmable time amplifier circuit comprises a phase detection circuit, a time preprocessing circuit, a rail-to-rail voltage comparator, a 3-8 decoder and a current biasing circuit. The phase detection circuit extracts a time interval of a step input signal and generates a pulse signal DN; the time preprocessing circuit controls the current source to charge and discharge the capacitor according to the pulse signal DN to generate two groups of ramp signals; the rail-to-rail voltage comparator realizes comparison in a full voltage range according to the two groups of input ramp signals; the 3-8 decoder provides a control signal for a capacitance control switch of the time preprocessing circuit; and the current bias circuit provides reference current bias for the time preprocessing circuit and the rail-to-rail voltage comparator. According to the invention, the input time interval can be accurately amplified, the time interval amplification of a high input range can be satisfied, the amplification factor programmable function can be realized, and the resolution and quantization input range of the assembly line TDC can be effectively improved.

The invention relates to a Fructus Amomi volatile oil soft capsule for alleviating chemotherapy induced intestinal mucosa damage, provides a use of Fructus Amomi volatile oil in the preparation of drugs for alleviating chemotherapy induced intestinal mucosa damage, and also provides a soft capsule for alleviating chemotherapy induced intestinal mucosa damage, and a preparation method thereof. The soft capsule comprises an effective component Fructus Amomi volatile oil, a matrix, and a soft capsule shell produced from gelatin, glycerin and water according to a ratio of (1-1.5):(0.2-0.8):(1-1.5). The Fructus Amomi volatile oil improves the body weight reduction, the appetite decrease and the diarrhea induced by a chemotherapy drug 5-FU, inhibits the rising of 5-FU induced inflammation factors, reduces the expression of cell apoptosis proteases, inhibits LPS from entering blood, and increases the expression of intestinal tight junction proteins in order to improve the F-5FU induced rat intestinal mucosa barrier damage. The Fructus Amomi volatile oil increase the intestinal probiotics, reduces the relative abundance of conditioned pathogens, improves the imbalance of 5-FU induced intestinal florae, and keeps the relative stability of the intestinal micro-ecology.

The invention discloses a CMOS fully-integrated electromagnetic detection radio frequency front-end sensor, which comprises a Hall sensor, a rotating current circuit, an instrument operational amplifier, a low-pass filter and a clock processing circuit, and is characterized in that the rotating current circuit is used for eliminating electromagnetic induction imbalance of the Hall sensor; the instrument operational amplifier is used for improving the load capacity of the circuit; the low-pass filter is used for realizing RC low-pass filtering of the circuit; and the clock processing circuit is used for outputting a high-level non-overlapped waveform clock, so that the influence caused by simultaneous conduction of the switches in the rotating current circuit is prevented. The CMOS technology is adopted, full integration of electromagnetic sensing is achieved, the sensor can be inserted between channels on the premise that the radio frequency performance is not affected, the chip area is not increased, cost is saved, and detection of the electromagnetic intensity between radio frequency front-end circuits is achieved.

The invention provides a level transfer system suitable for a multi-battery pack. The system comprises a battery pack, a first battery level transfer circuit, a top battery level transfer circuit anda second battery level transfer circuit, wherein the battery pack comprises a first battery, a second battery and a top battery; the first battery, the second battery and the top battery are connectedin series; the first battery level transfer circuit is connected with the cathode of the first battery and the anode of the top battery; the top battery level transfer circuit is connected with the cathode of the first battery, the cathode of the top battery and the anode of the top battery; and the second battery level transfer circuit is connected with the first battery level transfer circuit,the top battery level transfer circuit, the cathode of the first battery and the anode of the top battery. The level transfer system suitable for the multi-battery pack can realize the voltage level transfer of multiple batteries and obtain high-precision level transfer signals, and does not draw current from the corresponding battery during sampling, so as to avoid accelerating battery imbalancebecause the sampling circuit draws current from the respective corresponding battery.

The invention discloses a low-power-consumption switching algorithm applied to an SAR ADC, an adopted DAC capacitor array is divided into a positive-end capacitor array and a negative-end capacitor array, the positive end and the negative end of the positive-end capacitor array are equal, and each capacitor array comprises N-2 capacitors conforming to a binary relation and a dummy capacitor. All the capacitors have no split structure, and each capacitor is connected with a reference voltage or a GND or a common-mode voltage; when the highest-order capacitor is in the reference level reset state, a pole plate is connected with GND, and when the rest capacitors are in the reference level reset state, the pole plates are connected with reference voltage; for an input signal, a digital code isobtained after conversion of an N-bit SAR ADC. An extra complex structure does not need to be introduced, meanwhile, the offset of the comparator is reduced, and the capacitance area is saved.