A low-power-consumption switching algorithm applied to an SAR ADC

Abstract

The invention discloses a low-power-consumption switching algorithm applied to an SAR ADC, an adopted DAC capacitor array is divided into a positive-end capacitor array and a negative-end capacitor array, the positive end and the negative end of the positive-end capacitor array are equal, and each capacitor array comprises N-2 capacitors conforming to a binary relation and a dummy capacitor. All the capacitors have no split structure, and each capacitor is connected with a reference voltage or a GND or a common-mode voltage; when the highest-order capacitor is in the reference level reset state, a pole plate is connected with GND, and when the rest capacitors are in the reference level reset state, the pole plates are connected with reference voltage; for an input signal, a digital code isobtained after conversion of an N-bit SAR ADC. An extra complex structure does not need to be introduced, meanwhile, the offset of the comparator is reduced, and the capacitance area is saved.

Description

technical field [0001] The invention relates to a low-power switching algorithm applied to SAR ADC, and belongs to the technical field of capacitive DAC of SAR ADC. Background technique [0002] Analog-to-digital converters are key blocks in applications such as mobile devices, handheld medical diagnostic equipment, and wireless sensors, converting input analog signals into digital signals for processing. Due to the low power supply voltage brought about by the continuous reduction of CMOS process feature size and the battery limitation of power supply, it is inevitable for sensor network nodes to work under low voltage and low power consumption conditions. In this case, the SAR ADC is very suitable for low-voltage and low-power working occasions because there are few active devices in its structure and the requirements for analog circuits are not high. In the entire SAR ADC structure, the capacitive DAC network is an important part. Reducing the power consumption on the DA...

AI Technical Summary

Problems solved by technology

In the existing research, although the energy consumed by the DAC can be reduced to a low level, the focus on reducing the power consumption of the DAC often makes sacrifices in other aspects, such as the use of complex capacitor array structures, DAC output common A large change in the mode voltage will cause the comparator to generate dynamic offset, which will directly reduce the ENOB, SFDR and other performance indicators of the ADC.

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