37results about How to "Capacitor area is small" patented technology

A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging / discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging / discharging unit having a capacitor apparatus receives the control signal, determines whether to charge / discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging / discharging duty cycle of the charging / discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables / disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.

The invention discloses an improved 10-bit differential capacitance segmented coupling type DAC. The improved 10-bit differential capacitance segmented coupling type DAC comprises a positive secondary capacitance array, a positive coupling capacitor, a positive main capacitance array, a negative coupling capacitor, a negative main capacitance array and a sampling switch. The improved 10-bit differential capacitance segmented coupling type DAC uses a 12-bit differential DAC to realize the 10-bit differential DAC, the gain error of a 1-LSB is avoided, and the static property of the DAC is improved; and meanwhile, the positive secondary capacitance array, the positive main capacitance array, the negative secondary capacitance array and the negative main capacitance array realize the smaller capacitance through replacing the lowest capacitance in the DAC by unit capacitors in series, and the problem of oversize area due to improving the DAC precision is avoided. The improved 10-bit differential capacitance segmented coupling type DAC has good static property and takes up small area.

A heartbeat current signal conversion device, comprising a converter for converting a modulated optical signal into a current signal and transmitting same; a mixer for performing frequency conversion of a heartbeat current signal and a background photocurrent signal in the current signal, and then transmitting the modulated photocurrent signal, the frequency-converted heartbeat current signal and the frequency-converted background photocurrent signal in the current signal; a fully differential integrator for performing both positive integration and inverse integration on the modulated photocurrent signal, the frequency-converted heartbeat current signal and the frequency-converted background photocurrent signal, which are inputted, and then outputting a voltage signal. The fully differential integrator can improve the suppression of the heartbeat current signal conversion device to the common mode noise, and the linearity and the dynamic output range of the circuit. Moreover, the heartbeat current signal conversion device loop always forms a closed loop, and thus a direct output to the next-stage circuit can be achieved, eliminating an output buffer circuit, thereby reducing power consumption.

The invention relates to a successive approximation register analog-to-digital converter based on an asymmetric differential capacitor array. The successive approximation register analog-to-digital converter comprises a sample hold circuit, a comparer and a logic control module. The sample hold circuit comprises an asymmetric differential capacitor array and a sample switch module. According to the asymmetric differential capacitor array, a first input end is selectively electrically connected with a common-mode voltage end and a grounding terminal through a single pole double throw switch, asecond input end is electrically connected with an output end of the sample switch module, a third input end is electrically connected with a first output end of the logic control module, and the output end is electrically connected with the comparer. The first input end and the second input end of the sample switch module are electrically connected with an analog signal negative input end and ananalog signal positive input end. The output end of the comparer is electrically connected with the input end of the logic control module. According to the successive approximation register analog-to-digital converter provided by the invention, the power consumption can be effectively reduced, a capacitor area can be reduced, and the design difficulty can be reduced.

The present invention proposes a new radio frequency switch structure: each radio frequency switch includes a series branch and a parallel branch, the series branches through different radio frequency switches share an AC coupling capacitor, the parallel branch and the parallel branch in the same radio frequency switch The series branch shares an AC coupling capacitor, removes the blocking transistor and the AC coupling capacitor close to the ground in the parallel branch of the same radio frequency switch, does not need any negative voltage generating circuit, and can save more than 60% of the capacitor area compared with the traditional structure. The invention greatly reduces the area and cost of the chip while keeping the performance unchanged.