37results about How to "Capacitor area is small" patented technology

An object of the invention is to reduce an area occupied by a capacitor in a circuit in a semiconductor device, and to downsize a semiconductor device on which the capacitor and an organic memory are mounted. The organic memory and the capacitor, included in a peripheral circuit, in which the same material as the layer containing the organic compound used for the organic memory is used as a dielectric, are used. The peripheral circuit here means a circuit having at least a capacitor such as a resonance circuit, a power supply circuit, a boosting circuit, a DA converter, or a protective circuit. Further, a capacitor in which a semiconductor is used as a dielectric may be provided over the same substrate as well as the capacitor in which the same material as the layer containing the organic compound is used as a dielectric. In this case, it is desirable that the capacitor in which the same material as the layer containing the organic compound is used as a dielectric and the capacitor in which the semiconductor is used as a dielectric are connected to each other in parallel.

A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.

The invention discloses a binary capacitor array applied to a near-threshold SARADC and a switching method with low power consumption thereof. By means of special construction of a core module thereof, namely a DAC capacitor array, the power consumption of the DAC part in the conversion process of the SARADC can be greatly reduced in combination with a provided new switching algorithm. Only two reference levels are adopted in the algorithm, such that the algorithm is applied to designing the SARADC under near-threshold voltage. Compared with the area of the capacitor array required by the ordinary two-level capacitor switching technology, by means of flexible application of united, split and floating capacitor switching technologies, the total area of the capacitor array is reduced by 50%.

An acoustic sensor integrated MEMS microphone structure and a fabrication method thereof. A diaphragm (3e) and back-pole (7) which forms a condenser structure are formed on a substrate (1) having at least one recessed slot (1a) on the top. A sensitive electrode is formed on the substrate (1), the sensitive electrode comprising a fixed portion (3b) fixed on the substrate (1) via a sacrificial layer (2), and a bending portion (3a) inserted into the recessed slot (1a), wherein the bending portion and the side wall of the recessed slot form the condenser structure. The integrated structure integrates the condenser structure of the microphone and condenser structure of the acoustic sensor on a substrate (1), thereby increasing the integration level thereof and reducing the overall size of the package. Meanwhile, the microphone diaphragm (3e) and the sensitive electrode of the acoustic sensor can be fabricated on a same substrate (1) at the same time, from the same material, and using the same fabricating process to increase production efficiency.

The invention provides a high-speed switch time sequence for a successive approximation type analog-digital converter. The analog-digital converter comprises N orderly connected capacitor banks, each capacitor bank comprises a first capacitor array and a second capacitor array; the first capacitor bank is in a second connection state, and other capacitor banks are in a first connection state; the first connection state is as follows: a lower pole plate of the first capacitor array is connected with low-level voltage, a lower pole plate of the second capacitor array is connected with high-level voltage; the second connection state is as follows: the lower pole plate of the first capacitor array is connected with the high-level voltage, and the lower pole plate of the second capacitor array is connected with the low-level voltage; the high-speed switch time sequence further comprises a comparator, upper pole plates of all first capacitor arrays are connected with a first input end of the comparator, the upper pole plates of all second capacitor arrays are connected with a second input end of the comparator; a logic module is connected with the comparator and used for controlling the connection states of the capacitor banks according to internally stored time slot instructions. According to the time sequence provided by the invention, the capacitance area of the analog-digital converter is smaller, and the conversion speed is faster.

The invention discloses a capacitor array switching method applied to a low-voltage SAR ADC. An analog-to-digital converter based on the method comprises two N-bit sub analog-to-digital converters with the same structure, the method comprises the following steps: for the input signals VIP and VIN, after N comparisons, obtaining N-bit digital output codes, which are divided into a sampling stage and a conversion stage, wherein, in the sampling stage, the input signals VIP and VIN are respectively connected to top polar plates of an upper capacitor array and a lower capacitor array through sampling switches, and bottom polar plates of all capacitors of the upper capacitor array and bottom polar plates of all capacitors of the lower capacitor array are connected to corresponding voltages; and, in the conversion stage, the comparator performs MSB bit-to-LSB bit comparison on the voltages of the top polar plates of the upper and lower capacitor arrays to obtain corresponding digital codes,and the connection relationship of the capacitor bottom polar plates in the upper and lower capacitor arrays are controlled according to the digital codes, and the N-bit digital output codes are obtained through N times of comparison. According to the invention, the power consumption of the DAC part in the conversion process can be greatly reduced, only two reference levels are adopted, and the method is suitable for the design under the near threshold voltage.

The invention discloses a successive approximation type analog-to-digital converter and a three-level switching method thereof. The method comprises the steps that input signals VIP and VIN are compared N times to obtain an N-bit digital code, the N-bit digital code is divided into a sampling stage and a conversion stage, and in the sampling stage, the input signals VIP and VIN are connected to top polar plates of an upper capacitor array and a lower capacitor array through sampling switches respectively, and the bottom polar plate of each capacitor is connected to a corresponding voltage; inthe conversion stage, the comparator performs MSB bit-to-LSB bit comparison on the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array to obtain corresponding digital codes, and the connection relation of the capacitor bottom electrode plates in the capacitor arrays is controlled according to the digital codes; and comparing for N times is performed to obtain an N-bit digital code. According to the invention, the voltage change of +/-Vref is generated on the top plate of the capacitor for the first time, so that the reference voltage Vref of the capacitor array is reduced to half of the reference voltage Vref of a common method. Compared with a traditional switching algorithm, the method has the advantages that 99.79% of DAC power consumption isreduced, 75% of capacitance area is saved, common-mode level offset is only 0.5 LSB, and compromise of energy efficiency, area and common-mode level is achieved.

The invention discloses an improved 10-bit differential capacitance segmented coupling type DAC. The improved 10-bit differential capacitance segmented coupling type DAC comprises a positive secondary capacitance array, a positive coupling capacitor, a positive main capacitance array, a negative coupling capacitor, a negative main capacitance array and a sampling switch. The improved 10-bit differential capacitance segmented coupling type DAC uses a 12-bit differential DAC to realize the 10-bit differential DAC, the gain error of a 1-LSB is avoided, and the static property of the DAC is improved; and meanwhile, the positive secondary capacitance array, the positive main capacitance array, the negative secondary capacitance array and the negative main capacitance array realize the smaller capacitance through replacing the lowest capacitance in the DAC by unit capacitors in series, and the problem of oversize area due to improving the DAC precision is avoided. The improved 10-bit differential capacitance segmented coupling type DAC has good static property and takes up small area.

The invention discloses a two-level switching method applied to a successive approximation type analog-to-digital converter, which comprises the following steps of: comparing input signals VIP and VINfor N times to obtain an N-bit digital code, dividing the N-bit digital code into a sampling stage and a conversion stage, connecting the input signals VIP and VIN to top polar plates of an upper capacitor array and a lower capacitor array through a sampling switch in the sampling stage, and connecting each capacitor bottom polar plate to a corresponding voltage; in the conversion stage, enablingthe comparator to perform comparison from MSB bits to LSB bits on the voltages of the top polar plates of the upper and lower capacitor arrays to obtain corresponding digital codes so as to control the state of the bottom polar plate of each capacitor; and comparing for N times to obtain an N-bit digital code. The voltage change of +/-Vref is generated by switching for the first time, and the reference voltage Vref of the capacitor array is reduced to half of the reference voltage Vref of a common method; the introduced floating state is released within three-step conversion so as to simplifythe control logic; and only the LSB bit introduces a common mode level offset of 0.5 LSB. Compared with a traditional switching algorithm, the method has the advantages that the power consumption ofthe DAC is reduced by 99.51%, the capacitance area is saved by 75%, and the requirements on other modules of the ADC are not improved.

The invention discloses a deep trench isolated anti-crosstalk photoelectric detector, comprising a P-i-N laminar structure formed by sequentially laminating a P-type diffusion layer, a substrate layer and an N-type diffusion layer, wherein an isolation region is formed on the P-i-N laminar structure and divides the photo-surface of the P-i-N laminar structure into a plurality of quadrants. The photoelectric detector is characterized in that the isolation region is realized by adopting the following structure: a deep trench is made in the photo-surface of the P-i-N laminar structure, the cross section contour of the deep trench is matched with the outer contours of the plurality of quadrants, the axial direction of the deep trench is the same as the laminating direction of the P-i-N laminar structure, the depth of the deep trench reaches the upper end surface of the N-type diffusion layer, and the deep trench is filled with an insulating material. The photoelectric detector has the advantages: each quadrant of the quadrant photoelectric detector is effectively isolated, the area of the depletion layer of the photoelectric detector is reduced, the internal junction capacitance area is reduced, the RC time constant is reduced, and the response speed of a device is improved; and the deep trench is positioned in the body of the quadrant photoelectric detector, so that the influence of surface defects on the device is avoided.

An electronic device includes a power converter and a current detector that is disposed at at least one position out of a primary-side position and a secondary-side position for the power converter and detects a current flowing at the at least one position. A snubber circuit including a capacitor is directly connected in parallel to both ends of the current detector.

The invention discloses a low-power-consumption switching algorithm applied to an SAR ADC, an adopted DAC capacitor array is divided into a positive-end capacitor array and a negative-end capacitor array, the positive end and the negative end of the positive-end capacitor array are equal, and each capacitor array comprises N-2 capacitors conforming to a binary relation and a dummy capacitor. All the capacitors have no split structure, and each capacitor is connected with a reference voltage or a GND or a common-mode voltage; when the highest-order capacitor is in the reference level reset state, a pole plate is connected with GND, and when the rest capacitors are in the reference level reset state, the pole plates are connected with reference voltage; for an input signal, a digital code isobtained after conversion of an N-bit SAR ADC. An extra complex structure does not need to be introduced, meanwhile, the offset of the comparator is reduced, and the capacitance area is saved.

The invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a light-emitting area and a non-light-emitting area, and the array substrate comprises a substrate base plate; gate insulating layers which comprise a first gate insulating layer and a second gate insulating layer which are sequentially arranged on the substrate base plate;a storage capacitor which is located in the light-emitting area and comprises a first transparent electrode and a second transparent electrode, wherein the first transparent electrode is arranged between the first gate insulating layer and the second gate insulating layer, and the second transparent electrode is arranged on the second gate insulating layer and is opposite to the first transparentelectrode in position. According to the array substrate, the yield of products is increased, and the aperture opening ratio of pixels is increased. According to the display panel, the aperture openingratio of the pixels is large, and the resolution ratio during display is high.

The invention discloses a drive control circuit, a control method and a charge pump circuit. The drive control circuit is used for driving a switching tube, comprises a first capacitor and can be coupled with a first power supply and a second power supply. When the driving control circuit is in a first working state, the driving control circuit controls the first capacitor to be coupled with the first power supply and controls the first power supply to charge the first capacitor; when the driving control circuit is in a second working state, the driving control circuit controls the switching tube to be coupled with the second power supply and controls the second power supply to supply power to the switching tube; and when the driving control circuit is in a third working state, the driving control circuit controls the first capacitor to be coupled with the control end of the switching tube and controls the first capacitor to supply power to the switching tube. According to the drive control circuit, the control method and the charge pump circuit, the circuit energy consumption can be reduced, and the circuit efficiency can be improved.

The invention belongs to the technical field of analog circuits, and particularly relates to a low-pass filter for small-duty-ratio sampling. The filter comprises a capacitor and a resistor, and further comprises a sampling switch; the starting end of the sampling switch is connected with an input end, the other end of the sampling switch is grounded after passing through the resistor and the capacitor in sequence, and the connecting point of the resistor and the capacitor is an output end; and the duty ratio of the sampling switch is less than 1. The invention has the beneficial effects that the capacitance area can be greatly reduced, and the chip cost is saved.