Two-level switching method applied to successive approximation type analog-to-digital converter

Abstract

The invention discloses a two-level switching method applied to a successive approximation type analog-to-digital converter, which comprises the following steps of: comparing input signals VIP and VINfor N times to obtain an N-bit digital code, dividing the N-bit digital code into a sampling stage and a conversion stage, connecting the input signals VIP and VIN to top polar plates of an upper capacitor array and a lower capacitor array through a sampling switch in the sampling stage, and connecting each capacitor bottom polar plate to a corresponding voltage; in the conversion stage, enablingthe comparator to perform comparison from MSB bits to LSB bits on the voltages of the top polar plates of the upper and lower capacitor arrays to obtain corresponding digital codes so as to control the state of the bottom polar plate of each capacitor; and comparing for N times to obtain an N-bit digital code. The voltage change of + / -Vref is generated by switching for the first time, and the reference voltage Vref of the capacitor array is reduced to half of the reference voltage Vref of a common method; the introduced floating state is released within three-step conversion so as to simplifythe control logic; and only the LSB bit introduces a common mode level offset of 0.5 LSB. Compared with a traditional switching algorithm, the method has the advantages that the power consumption ofthe DAC is reduced by 99.51%, the capacitance area is saved by 75%, and the requirements on other modules of the ADC are not improved.

Description

technical field [0001] The invention relates to a two-level switching method applied to a successive approximation analog-to-digital converter, and belongs to the technical field of charge redistribution CDAC of SARADC. Background technique [0002] Charge redistribution SARADC is widely used in portable devices, medical devices, and the Internet of Things due to its high degree of digitalization, compatibility with advanced processes, and high energy efficiency. Among its various modules, CDAC is the most energy-consuming part. When SARADC performs analog-to-digital conversion, CDAC will perform capacitor switching to generate the required reference voltage, and dynamic switching power consumption will be generated during the process. [0003] In the existing research, a variety of switching algorithms have been proposed to reduce the switching power consumption of CDAC. However, they increase reset power consumption while reducing switching power consumption, common-mode ...

AI Technical Summary

Problems solved by technology

[0007] Technical problem: the technical problem to be solved by the present invention is, for the design of SARADC, proposes a kind of two-level switch method that is applied to the successive approximation analog-to-digital converter, only uses two levels to the energy efficiency ( Including reset power consumption), capacitor area, common-mode level shift and required control logic complexity to make a better compromise, so that this switching algorithm will not have a high impact on other modules of the ADC while reducing CDAC power consumption Require

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