13 results about "Cmos switch" patented technology

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

The application relates to the technical field of integrated circuit design, and particularly discloses a pre-charging low-leakage control circuit and method, which comprises the following: an MOS switch, the source electrode of which is electrically connected with the input end of a pre-charging buffer, and the drain electrode of which is electrically connected with the output end of the pre-charging buffer; the MOS switch is an NMOS switch, a PMOS switch or a CMOS switch; a control switch network, which comprises a plurality of control switches, one end of one of the control switches being electrically connected with the input end of a switch capacitor circuit; and the control switch network is used for connecting the back gate of the MOS switch to different working nodes according to the working phase of the control circuit. According to the application, the back gate of the MOS switch can be connected to different working nodes according to the working phase of the control circuit, so that when the MOS switch is turned on, the back gate always maintains the same potential as the input end of the pre-charging buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.

The invention discloses a dual-function metasurface device applied to passive radio frequency energy collection and backscatter communication, which comprises three dielectric substrates stacked through positioning holes, and is characterized in that each dielectric substrate is printed with a first metal layer, a second metal layer and a third metal layer which are sequentially arranged from top to bottom, the first metal layer is of a first orthogonal grating structure loaded with a plurality of CMOS switches, the second metal layer is a phase modulation layer composed of a plurality of independently controllable resonance units, the third metal layer is of a second orthogonal grating structure, and the grating orientation of the third metal layer is orthogonal to that of the first orthogonal grating structure. The invention also discloses a backscatter communication system. In the communication process, a power amplifier is not needed, only micro-watt power consumption of switch switching is consumed, battery-free operation is achieved in combination with environment energy collection, the bottleneck of direct path interference in traditional environment backscatter communication is overcome through polarization isolation, and a farther reliable communication distance can be obtained under the same transmitting power.

Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.

This invention belongs to the field of analog integrated circuits and memory technology, and relates to a multi-value RRAM read / write circuit and its method. The multi-value RRAM read / write circuit includes an RRAM control unit, a low-dropout linear regulator, a standard resistor unit, a leakage current sampling unit, a read / write conversion unit, a CMOS switch, and an operational amplifier. The low-dropout linear regulator provides a stable gate voltage for the RRAM control unit and the standard resistor unit. The standard resistor unit adjusts the resistance value of the RRAM. The leakage current sampling unit samples and compensates for leakage current. The read / write conversion unit receives a read / write conversion signal and controls the CMOS switch based on the signal to switch between read and write modes of the multi-value RRAM read / write circuit. The operational amplifier is connected in write mode to maintain voltage stability across the RRAM. This invention can sample and compensate for leakage current, greatly reducing the impact of leakage current on RRAM read / write operations.

The invention belongs to the technical field of analog integrated circuit design, circuit control and memories, and provides a D flip-flop circuit with saving and loading functions. The D flip-flop circuit is in the same physical space, switching of a storage state circuit and a loading state circuit is achieved through a CMOS switch, and in the storage state, voltage is applied to two RRAM devices through the CMOS switch and an MOS tube, so that the two RRAM devices are in a low-resistance state and a high-resistance state respectively; and in a loading state, the CMOS switch is used for controlling the on-off of the circuit, and the voltage at the two ends of the RRAM device is read. The D flip-flop circuit makes up the defects of functions of an existing nonvolatile D flip-flop, state storage and loading are achieved, meanwhile, through the independent state storage circuit, it is avoided that RRAM state switching affects the speed of the D flip-flop, data are not lost after power failure, and the working current of an RRAM is prevented from increasing the power consumption of the D flip-flop.

The invention discloses a bandwidth improvement method and circuit based on a switch well capacitor. The method comprises the following steps: obtaining the highest withstand voltage value of a deep N well of an MOS tube in a target CMOS; determining a high-voltage signal applied to the corresponding isolation end based on the highest withstand voltage value; wherein the high-voltage signal is used for generating reverse bias voltage on a to-ground PN junction formed at the deep N well; and generating a high-voltage signal by using the high-voltage control module, and accessing the high-voltage signal to the isolation end, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS tube. According to the invention, the well capacitance can be reduced, and the signal bandwidth of the target CMOS switch is further improved.

A first pull-up switch 106 and a second pull-down switch 112 are CMOS switches driven by a first input signal INp and an output #INp of a first inversion buffer 102. A second pull-up switch 110 and a first pull-down switch 108 are CMOS switches driven by a second input signal INn and an output #INn of a second inversion buffer 104. A latch circuit 114 is connected to a first node n1 and a second node n2. A first output buffer 116 and a second output buffer 118 receive a voltage Vn1 of the first node n1 and a voltage Vn2 of the second node n2.

The invention relates to the technical field of integrated circuit design, and particularly discloses a pre-charging low-leakage control circuit and method, the control circuit comprises an MOS switch, the source electrode of the MOS switch is electrically connected with the input end of a pre-charging module, the drain electrode of the MOS switch is electrically connected with the output end of a pre-charging buffer, and the MOS switch is an NMOS switch or a PMOS switch or a CMOS switch; and the control switch network comprises a plurality of control switches, one end of one control switch is electrically connected with the input end of the switched capacitor circuit, and the control switch network is used for connecting the back gate of the MOS switch to different working nodes according to the working phase of the pre-charging module. The back gate of the MOS switch can be connected to different working nodes according to the working phase of the pre-charging module, it is guaranteed that when the MOS switch is turned on, the back gate of the MOS switch and the input end of the pre-charging module keep the same potential all the time, and then the influence of the back gate effect on the pre-charging module is reduced or eliminated.

Embodiments of the present disclosure relate to a charge pump circuit configured for positive and negative voltage generation. A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between ground and a positive supply voltage, the intermediate node generating a first signal oscillating between a first voltage and a second voltage. The level shift circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between the first voltage and a third voltage. The CMOS switching circuit includes: a first transistor having a source coupled to an input; and a second transistor having a source coupled to the output and having a gate coupled to receive a second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive a first clock signal. When the pump is positive, the first voltage is twice the second voltage, and the third voltage is grounded. During negative pumping, the first voltage and the third voltage are opposite in polarity, and the second voltage is grounded.

The application discloses a charge pump phase-locked loop and relates to the field of phase-locked loops. In order to solve the problem that a traditional charge pump phase-locked loop cannot effectively reduce VCO output phase noise while ensuring normal operation of the charge pump, the application provides a charge pump phase-locked loop. The charge pump phase-locked loop is structured by a new type of analog phase detector + charge pump, and the difference between mirror currents of the charge pump generated by a reference clock signal and a feedback clock signal in different phase stages is used to charge / discharge a loop filter. The charge pump phase-locked loop can meet stable control of a control voltage of the loop filter, and CMOS switches are not needed. Therefore, the adverse effects caused by clock feedthrough and charge injection can be obviously reduced, and the normal operation of the charge pump phase-locked loop is not affected.

The invention belongs to the technical field of analog integrated circuits and memories, and relates to a multi-valued RRAM read-write circuit and a read-write method thereof.The multi-valued RRAM read-write circuit comprises an RRAM control unit, a low dropout regulator, a standard resistor unit, a leakage current sampling unit, a read-write conversion unit, a CMOS switch and an operational amplifier; the low dropout linear regulator is used for providing stable grid voltage for the RRAM control unit and the standard resistor unit, the standard resistor unit is used for adjusting the resistance value of the RRAM, the leakage current sampling unit is used for sampling and compensating leakage current, and the read-write conversion unit is used for receiving a read-write conversion signal and sending the read-write conversion signal to the RRAM control unit. The CMOS switch is controlled based on the read-write conversion signal so as to switch a read mode or a write mode of the multi-valued RRAM read-write circuit, and the operational amplifier is connected in the write mode and used for maintaining the voltage at the two ends of the RRAM to be stable. According to the invention, leakage current sampling and compensation can be carried out, and the influence of leakage current on RRAM read-write is greatly reduced.