Nine-stage ten-bit pipelined ADC circuit

A pipeline and circuit technology, applied in the direction of analog/digital conversion calibration/test, analog-to-digital converter, etc., can solve problems such as capacitance mismatch error, comparator offset, switch nonlinearity, etc.

Inactive Publication Date: 2014-07-02
XINXIANG UNIV
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  • Abstract
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AI Technical Summary

Problems solved by technology

The main error sources in the pipeline ADC include switch nonlinearity, comparator offset, and op amp non-ideal characteristics: including finite gain error, offset, etc., capacitance mismatch error, these factors will bring MDAC gain error, and thermal noise, The influence of non-ideal factors such as clock feedthrough makes the transmission characteristics of the pipeline ADC non-ideal

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  • Nine-stage ten-bit pipelined ADC circuit
  • Nine-stage ten-bit pipelined ADC circuit
  • Nine-stage ten-bit pipelined ADC circuit

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Embodiment Construction

[0043] The pipeline ADC involved in the present invention adopts the pipeline ADC under 0.6μmBiCMOS technology, the pipeline ADC system adopts 2.5V power supply, the input range of the analog signal is -1V-1V, and the conversion rate is 2M / s. The pipeline ADC includes a sampling and holding circuit, a 9-level 10-bit pipeline unit processing module, an external clock generation circuit module, and a delay and digital correction circuit module.

[0044] The overall circuit design of the system is as figure 1 shown. The input analog quantity VIN passes through the sample and hold circuit (S / H), and is processed by 9-stage pipeline units. After the two-digit digital output of each stage unit is "aligned" in time by the delay module (DELAY), it is input in parallel to the digital correction module ( Digital Correction), generating 10-bit pipeline ADC output D9-D0. Among them, the external 4MHz clock CLK-IN generates 4-phase 2MHz non-overlapping clock output through the non-overla...

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Abstract

The invention discloses a nine-stage ten-bit pipelined ADC circuit. During the designing of a modular circuit, to avoid nonlinearity caused by on-resistance change of an ordinary CMOS switch, firstly, a nine-stage pipelined unit is adopted for the overall structure of an ADC, identical 1.5-bit structures are adopted by all the nine stages, so that modularization of the circuit is improved, and the figure adjustment technique is adopted to reduce the designing requirements of a sub-analog-digital converter (SubADC) and reduce the influence of non-ideal factors; secondly, optimal design is conducted on the modular circuit to reduce the error of the ADC. According to the nine-stage ten-bit pipelined ADC circuit, due to the fact that a single-capacitor sampling hold circuit and a bootstrapped switch are used, sampling linearity and accuracy are improved; due to the fact that an operational amplifier detuning eliminated type switched capacitor MDAC circuit structure is adopted, margin amplification accuracy is improved; a full-adder circuit is used for achieving figure adjustment, and the structure is simple.

Description

technical field [0001] The invention relates to a pipeline ADC circuit, in particular to a nine-stage ten-bit pipeline ADC circuit. Background technique [0002] Since the 1990s, the application of digital technology has become more and more extensive. There are several reasons why digital technology is superior to traditional analog technology: first, because it is insensitive to interference such as noise and power supply changes, digital processing can achieve higher precision than analog processing; second, digital signals can Convenient storage without distortion and loss of integrity; third, the digital signal processing method enables more complex processing algorithms to be realized more conveniently, and is also conducive to product upgrades and replacements; fourth, the development of computer-aided design technology It enables digital technology to realize design automation very conveniently and effectively; fifth, and more importantly, the development of large-s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12H03M1/10
Inventor 贾蒙陈波张烨姚鹏左艳君
Owner XINXIANG UNIV
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