Method and device for reducing offset voltage of Hall integrated circuit

An offset voltage, integrated circuit technology, applied in circuits, electrical components, electric solid devices, etc., can solve the problems of unpredictable and controllable offset voltage, and achieve good consistency, small Hall output voltage offset, and good matching. Effect

Inactive Publication Date: 2011-12-28
WUXI POWERSILICON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But in practice even with the figure 2 The layout design of the symmetrical array Hall cell still has some factors that cause the offset voltage to be unpredictable and controllable

Method used

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  • Method and device for reducing offset voltage of Hall integrated circuit
  • Method and device for reducing offset voltage of Hall integrated circuit
  • Method and device for reducing offset voltage of Hall integrated circuit

Examples

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no. 1 example

[0033] Fig. 6 shows a sectional view along the direction A-A of Fig. 5 . The same number in the figure represents the same area. A lightly doped N-type epitaxial layer 2 is grown on a semiconductor P-type base substrate 1 , and the epitaxial layer 2 is separated by heavily doped P-type isolation bands 3 into isolated epitaxial islands, that is, Hall cells 4 . Four identical Hall cells 4 connected in parallel form a Hall sensor and are located in the middle of the chip (FIG. 5).

no. 2 example

[0035] Figure 8 shows the layout design method and connection mode of the Hall unit 4 of the second embodiment. Compared with the first embodiment, the Hall unit 4 is rotated at an angle of 45 degrees, and the wider part is not shown in the figure. Epitaxial layer 2 and isolation zone 3.

no. 3 example

[0037] Figure 9 shows the layout design method and connection mode of the Hall unit 4 of the third embodiment. Compared with the second embodiment, it is only composed of three Hall units 4, and the Hall unit 4 is symmetrical to the center of a parallelogram Balanced setting, the wider epitaxial layer 2 and the isolation zone 3 are not drawn in the figure.

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Abstract

A method for reducing the offset voltage of the Hall integrated circuit is to place the Hall cell array at the center of the chip, place other circuit devices serving the Hall cell around the Hall cell array, and connect the Hall cells in parallel. The periphery of each Hall cell is surrounded by isolation bands and epitaxial layers formed by heavy doping. The related device includes a semiconductor P-type base substrate, and a lightly doped semiconductor N-type epitaxial layer grown on the semiconductor P-type base substrate. There is also a heavily doped semiconductor P-type isolation zone on the semiconductor N-type epitaxial layer, which divides the semiconductor N-type epitaxial layer into at least three isolated Hall cells, and the Hall cells are symmetrically arranged in the center array. The invention can make the Hall device be affected by the stress and pressure of the edge of the chip to be consistent, so that the offset voltage of the Hall unit is less affected by other devices around the Hall unit, and the Hall unit is affected by the deviation of the manufacturing process Consistent, better matching.

Description

【Technical field】 [0001] The present invention relates to the improvement of semiconductor integrated circuits, especially Hall devices. More specifically, it relates to a layout design method and device for reducing the offset voltage of a Hall device integrated in an integrated circuit. 【Background technique】 [0002] Hall devices based on the principle of the Hall effect are mainly used as magnetic sensors. As we all know, the advantage of Hall devices made of silicon materials is that their manufacturing technology is compatible with microelectronic integrated circuit technology, and can be combined with various protection circuits (such as adjustment, compensation and protection circuits) and signal processing circuits (such as amplifiers, Schmitt trigger, band-pass filter and output circuit) etc. are integrated together to form various functional circuits, realizing mass production and greatly reducing production costs; output signals can be directly used by computers...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/22
Inventor 管慧陈俊
Owner WUXI POWERSILICON TECH
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