55results about How to "No static power" patented technology

The invention discloses a pre-amplifying latch comparator with low detuning. The pre-amplifying latch comparator with the low detuning comprises a base pre-amplifying latch comparator, a detuning compensation geminate transistor, a detuning calibration switch and a detuning calibration control circuit. The base pre-amplifying latch comparator comprises a primary pre-amplifier and a secondary latch. The detuning compensation geminate transistor comprises a detuning adjusting transistor, the detuning adjusting transistor is connected to the output end of the pre-amplifier in parallel, and the detuning voltage of the whole comparator is regulated by changing a grid voltage of the detuning adjusting transistor. A digital bidirectional shifter is adopted by the detuning calibration control circuit to store detuning information and control the detuning calibration control circuit to carry out detuning calibration. According to the pre-amplifying latch comparator with the low detuning, the detuning calibration control circuit based on digital storage and control is added based on an existing pre-amplifying latch comparator, the detuning of the pre-amplifying latch comparator can be reduced to one nth of original detuning, and the pre-amplifying latch comparator after calibration reduces the detuning greatly.

The invention provides a low-power-consumption self-cutting-off circuit and a level switching circuit of the low-power-consumption self-cutting-off circuit. When a voltage cutting-off signal generated by a working circuit hops from a low level to a high level, voltage domain switching of the signal is conducted through the level switching circuit, the signal is sent to the clock end of a trigger, and then the output end of the trigger outputs high voltage to a power circuit so that the voltage provided for the working circuit by the power circuit can be cut off. After the voltage supplying is cut off, the level of the voltage cutting-off signal of the working circuit slowly returns to zero, and the level of the signal output by the level switching circuit is kept being clamped at a low level. A low level efficient signal of a power-on reset signal is awakened to be connected to the trigger through an and gate and is reset so that the power circuit can be controlled to normally provide the voltage for the working circuit. Under the condition that a power supply is shut down, according to the low-power-consumption self-cutting-off circuit and the level switching circuit of the low-power-consumption self-cutting-off circuit, the level of a power cutting-off signal can be kept unchanged, therefore, the off-position is kept, and power consumption is reduced. Meanwhile, no static power consumption is produced by the circuits when the circuits work normally.

The invention provides a bootstrap capacitor power failure restoring circuit and a switch power source circuit. The bootstrap capacitor power failure restoring circuit comprises a bootstrap capacitor, a second switch tube, a logic signal circuit, an undervoltage detecting circuit, a first control circuit and a second control circuit. When voltage at two ends of the bootstrap capacitor is in undervoltage state, on and off of the first switch tube are controlled according to a first control signal, and meanwhile, the second switch tube is kept off. When voltage of two ends of the bootstrap capacitor is in undervoltage state, the first switch tube is switched off, and when effective time of the first control signal is up to a first preset time, the second switch tube is conducted, the bootstrap capacitor is started to be charged, and the second switch tube is switched off after a second preset time. The bootstrap capacitor is charged by circulating the above steps. The switch power source circuit comprises a power-level circuit and the bootstrap capacitor power failure restoring circuit.

The invention discloses a gate drive circuit without static power consumption, and belongs to the technical field of electronic circuits. A floating power supply ground module is used for generating afloating power supply ground signal and a high side reset signal, wherein a low voltage-high voltage level shifting module is used for shifting a low voltage driving signal of a front stage to a highvoltage side to control a high side power transistor; a high voltage-low voltage level shifting module is used for feeding back a high side signal of the floating power supply to a low side, and closing an input stage in the low voltage-high voltage level shift module through a logic control module to ensure that the gate drive circuit provided by the invention is free from static power consumption; and a drive output module drives the high side power transistor and a low side power transistor respectively by using the high side drive output unit and the low side drive output unit, and the logic control module provides logic control. The gate drive circuit is free from static power consumption, and meanwhile the problem of voltage resistance of a gate source is solved well.

The invention discloses a low-power-consumption time-delaying power-down circuit of an electric automobile and a control method. The method comprises the steps that an enabling signal identifying circuit collects multiple power-on and power-off enabling signals of different types, and when it is identified that the states of all collected signals are invalid states, power-down signals are output to a delaying time judgment circuit; the delaying time judgment circuit receives the power-down signals which are sent by the enabling signal identifying circuit and conducts time delaying, and outputsthe power-down signals to a power source switch driving circuit after delaying time is up; the power source switch driving circuit sends power-down driving signals to a power source switch executioncircuit; the power source switch execution circuit switches off the circuit according to the power-down driving signals which are sent by the power source switch driving circuit. According to the low-power-consumption time-delaying power-down circuit of the electric automobile and the control method, static-state power consumption and time-delaying power-down functions can be achieved at the sametime, after power-down, static-state power consumption does not exist at all, and compared with an existing power source management chip scheme, static-state power consumption is lower in cost, static-state power consumption is smaller, and more power is saved.

The invention discloses a read data signal processing circuit for a DDR (Double Data Rate) memory, and a read data processing method. The read data signal processing circuit comprises a sampling and receiving module and a pulse width the testing module, wherein the sampling and receiving module is connected with the pulse width the sting module when a coding numerical value corresponding to a digital control signal TD [n-1:0] corresponds to the period of a data pulse selection signal DQS; and according to the digital control signal TD [n-1:0], 1/4 of the period of the data pulse selection signal DQS is additionally delayed for the data pulse selection signal DQS, so that a maximum time sampling window can be obtained when the data pulse selection signal DQS samples a data signal DQ. The technical scheme is controlled and processed by digital coding, and instant work can be realized.

The invention relates to a power-on reset circuit being fee of static power consumption. The power-on reset circuit includes a voltage detection circuit, a hysteresis comparison circuit and a voltage shaping circuit which are sequentially and electrically connected; the voltage detection circuit includes a transistor MN1, a transistor MN2, a transistor MP1 and a transistor MP2; the transistor MN1, the transistor MP1, the transistor MN2 and the transistor MP2 are connected in series, the drain of the next transistor is connected with the source of the previous transistor; the drain of the transistor MN1 and the source of the transistor MP1 are connected with the hysteresis comparison circuit; the hysteresis comparison circuit converts the output signal of the voltage detection circuit into a rectangular wave; and the voltage shaping circuit is used for eliminating tiny perturbations in the rectangular wave, and the output end of the voltage shaping circuit is the output end of the power-on reset circuit. The static power consumption problem is solved by selecting a P-channel MOS transistor, the power-on reset function is realized while the static power consumption is eliminated, and the power-on reset circuit can be widely applied to the low power consumption filed of handheld devices.

The invention provides a full-MOS voltage and temperature monitoring method and monitoring circuit. The circuit comprises two annular oscillators RO1 and RO2, two time-digital converters TDC1 and TDC2, a temperature mapping module, a voltage mapping module, a reference clock frequency divider module and two compensation modules, wherein a reference block is provided by a crystal oscillator, poweris supplied to the annular oscillator RO1 through a core-domain power supply voltage VDD_CORE, power is supplied to the annular oscillator RO2 through a battery voltage VBAT, the reference clock is separately connected to the TDC1 and the TDC2 through the frequency divider, and output terminals of the TDC1 and the TDC2 are respectively connected to the temperature mapping module and the voltage mapping module. According to the method and circuit, real full MOS can be realized, extra masks are avoided, effective calibration of the PVT is realized, the monitoring precision is improved, and the method and the circuit are advantageous in that the structure is simple, the area is small, and static power consumption is avoided.

The invention relates to a buzzer driving circuit and a corresponding buzzer driving method. The driving circuit comprises a control circuit module, a boost circuit module and a switch driving circuitmodule. The control circuit module is used for controlling the working state of the boost circuit module and the switch driving circuit module. The boost circuit module is used for boosting the voltage supplied by the voltage source and transmitting the boosted voltage to the switch driving circuit module. The switch driving circuit module controls the buzzer according to the signal outputted bythe control module. With application of the buzzer driving circuit and the corresponding buzzer driving method, the buzzer can be controlled effectively; meanwhile, functional control of the circuit can be realized by only using the common inductors and components in the circuit, the cost is low, the device volume is small, the current performance is stable and the buzzer works stably. When the driving circuit is in the standby state, the boost circuit module and the switch driving circuit module have no static power consumption, and thus the power consumption is low.

The invention provides a zero static power consumption undervoltage detection circuit, which comprises PMOS tubes PM1, PM2 and PM3; NMOS tubes NM1 and NM2; phase inverters I1 and I2; and a capacitor CP and a power voltage VDD, and can be applied to an SOC chip or an analog chip to provide a reset signal in a power-off process. The undervoltage detection circuit has no static power consumption under a normal working state, and a threshold value of the power voltage can be set to be extremely low; and the undervoltage detection circuit can be applied in a low-voltage environment.

The invention discloses an energy-saving switch power supply with a self-locking function. The energy-saving switch power supply comprises a direct-current power supply circuit, a switch control circuit, a switch S1, a switch S2, a resistor R2, a relay K and a triode V1, wherein one end of the button switch S1 is connected witha resistor R1, a contact K-1 of the relay K, the button switch S2 and a power supply U1; the other end of the switch S1 is connected with the other end of the contact K-1 of the relay K, a collector electrode of the triode V1 and a base electrode of a triode V2; a collector electrode of the triode V2 is connected with the other end of the resistor R1 and the relay K; the other end of the relay K is connected with a collector electrode of the triode V3. According to the energy-saving switch power supply with the self-locking function provided by the invention, the design of a PCB (Printed Circuit Board) circuit in the switch power supply is improved, and the self-locking function is realized by utilizing self contacts of the relay, so that the circuits have no static power consumption when being mis-triggered, and are applicable to alternating-current and direct-current loads so as to have the advantages of electric energy conservation, wide application range, and convenience in use.

The invention discloses a chip routing selection circuit free of quiescent dissipation. The electrode D of a PMOS tube T1 is connected with a circuit control end and a circuit controlled end, and the electrode G of the PMOS tube T1 is connected with a capacitor C1 and one end of a resistor R2, and is further connected with the electrode D of the PMOS tube T1. The electrode S of the PMOS tube T1 is connected with a resistor R1 in series and is connected with a VDD, the electrode S and the electrode G of a PMOS tube T4 and the electrode S of a PMOS tube T2. The other end of the capacitor C1 is connected with the GND. The other end of the resistor R2 is simultaneously connected with the PMOS tube T2 and the electrode D of an NMOS tube T3, the electrode S of the NMOS tube T3 is connected with the GND, and the PMOS tube T2 is connected with the electrode G of the NMOS tube T3 and is connected with the circuit controlled end. One connecting wire is needed only when the circuit control end is connected with the GND, and the quiescent dissipation does not exist whether the circuit control end is connected with the GND or suspended.

A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal. The second circuit portion includes a second clamp circuit, wherein the second circuit portion is biased through the second clamp circuit and the first node. The second circuit portion provides a first internal bias for the first circuit portion and the first circuit portion provides a second internal bias for the second circuit portion. This high voltage level-shifter provides level shifting a low voltage signal (<5V) to a high voltage signal (˜40V), with no static power dissipation while still protecting all devices.

The invention provides an undervoltage detection circuit applicable to a low voltage environment, which comprises a PMOS transistor PM1, NMOS transistors NM1 and NM2, inverters I1 and I2, a capacitorCP and power supply voltage VDD, wherein one end of the capacitor CP is connected with the power supply voltage VDD and the other end is connected with the source end of the NM2; and the NM2 is a low-threshold NMOS transistor. The circuit provided in the invention can be applied in a low voltage environment and has no static power consumption under a normal operating condition.

The present invention discloses a level conversion circuit. The level conversion circuit comprises a voltage reduction module, a feedback module, a reverse module and a sampling module. The voltage reduction module comprises the input port of the level conversion circuit and a power supply port and an output port. The feedback module comprises a power supply port and the input and output ports of the feedback module, wherein the input port of the feedback module is connected with the output port of the voltage reduction module. The feedback module is earthed through an earthing port. The reverse module comprises a power supply port and input and output ports of the reverse module, wherein the input port of the reverse module is connected with the output port of the feedback module. The reverse module is earthed through the earthing port. The output of the reverse module is the whole output port of the level conversion circuit. The sampling module is connected with the output port of the voltage reduction module and the output port of the reverse module through two ports, and is earthed through a port. The level conversion circuit uses low-voltage tubes, and all the CMOS devices allow high-voltage domain level to translate low-voltage domain level.

The invention relates to the field of integrated circuit design, in particular to a starting circuit and a current source with the same. In the embodiment, the whole starting circuit only needs six MOS (metal oxide semiconductor) tubes with small area, thereby being simple in structure. Compared with other starting circuits, the starting circuit has the advantages that the area of chips is reduced, the starting circuit is high in operating reliability and can be quickly started, the conductive MOS tubes can pull a suspension potential point to low potential to switch off the starting circuit only after a current source unit is in normal operation, so that the whole starting and switch-off process is short, and nanosecond scale can be reached at the soonest, starting time can be regulated according to needs of an electronic system, and the starting circuit does not need static power consumption after the system enters a stable operation state.