High-energy-efficiency full-dynamic comparator applied to SAR ADC

Abstract

The invention discloses a high-energy-efficiency full-dynamic comparator applied to an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-energy-efficiency full-dynamic comparator comprises a pre-amplification circuit, a latch circuit and a pre-amplification stage control circuit which are in three-stage cascade connection with an input tube, the pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit after the latch circuit outputs a comparison result. Meanwhile, high-level or low-level setting is carried out on the output node of the pre-amplification circuit according to the comparison result, so that unnecessary amplification operation of the pre-amplification circuit after comparison is completed is avoided, a latchresult is kept, and the power consumption of the comparator is further reduced on the premise of not influencing the performance of the comparator. In addition, due to the cascade amplification characteristic of the pre-amplification circuit, the pre-amplification gain is improved. Meanwhile, the equivalent noise of the pre-amplification stage and the latch stage at the input end is reduced; a single-phase clock signal is adopted to control the circuit, so that the clock load is reduced; circuits in all working stages have no static power consumption.

Description

technical field [0001] The invention relates to the field of digital-analog hybrid integrated circuit design, in particular to a high-energy-efficiency full-dynamic comparator design suitable for SAR ADC. Background technique [0002] In recent years, with the development of VLSI, wireless communication, and Internet of Things technologies, wireless sensor networks have been widely used, such as biomedical systems, environmental monitoring, mobile devices, and wearable devices. In these applications, the external signal collected by the wireless sensor needs to be converted into a digital signal through an analog-to-digital converter. Wireless sensor network nodes are generally powered by small batteries or energy harvesting systems. In order to prolong the working time of devices, it is meaningful to design low power consumption for ADCs. SAR ADC is widely used in low power consumption design because of its natural advantage of no op amp structure. The comparator is a key...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a high-energy-efficiency full-dynamic comparator suitable for SAR ADC, and solve the problem that the pre-amplification stage in the cascaded input comparator still continues after the latch stage outputs the comparison result. The problem of doing unnecessary work, further reducing the power consumption generated by the comparator

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